Pulse Output Circuit With Edge Delay for Duty Cycle Stability
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Solution Overview
Problem
Existing pulse signal sending circuits face challenges in maintaining consistent pulse width and duty cycle due to unequal rising and falling lag times, leading to inappropriate signal transmission and increased circuit complexity, which results in larger chip sizes.
Innovation Solution
A pulse signal sending circuit is designed with an output transistor, a CMOS inverter circuit, and a delay circuit that delays the rising or falling of input pulse signals, ensuring equal rising and falling lag times by adjusting the delay time, thus maintaining consistent pulse width and duty cycle, and allowing for accurate slope control of output waveforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a pulse width adjusting circuit is added to maintain pulse width and duty cycle, then signal transmission accuracy is improved, but circuit scale and chip size increase
Solution Approach 1:
The patent introduces a delay circuit as an intermediary component that delays either the rising or falling edge of the input pulse signal. This delay circuit acts as a mediator between the input signal and the inverter circuit, adjusting the timing of one edge to compensate for the unequal rise and fall times, thereby maintaining accurate pulse width and duty cycle without requiring a complex pulse width adjusting circuit
Solution Approach 2:
The patent changes the timing parameter of the pulse signal by introducing a controllable delay in one of the edges (rising or falling). By adjusting the delay time parameter in the delay circuit, the circuit compensates for the inherent asymmetry in rise and fall times, maintaining the desired pulse width and duty cycle with a simple parameter adjustment rather than a complex circuit
2Object-affected harmful factors
If slope control is implemented to reduce EMI, then electromagnetic interference is reduced, but pulse width and duty cycle accuracy deteriorate
Solution Approach 1:
The patent applies preliminary anti-action by pre-delaying one edge of the pulse signal before it enters the inverter circuit. This pre-delay compensates for the upcoming asymmetry in rise and fall times caused by slope control, ensuring that the final output pulse maintains the correct width and duty cycle despite the slope control measures being in place
3Manufacturing precision
If rising and falling lag times are made equal, then pulse width and duty cycle are maintained, but circuit complexity increases
Solution Approach 1:
The patent extracts only the essential function needed to equalize rise and fall times by removing the complex pulse width adjusting circuit and retaining only a simple delay circuit. This delay circuit is inserted into one signal path to create the necessary time difference, achieving the equalization of effective rise and fall times with minimal additional circuitry
Data Source
Figure 1
Figure 2A~2C
Figure 3A~3B
AI summary
A pulse signal sending circuit (10) that outputs pulse signals from an output terminal includes: an output transistor (11); an inverter circuit (12); and a delay circuit (13). The output transistor includes a drain terminal connected to the output terminal. The inverter circuit is connected to a gate terminal of the output transistor and outputs a signal to be input to the gate terminal of the output transistor. The delay circuit receives a pulse signal as an input and delays rising or falling of the input pulse signal. The pulse signal delayed by the delay circuit is input to the inverter circuit.