Buffer Circuit Voltage Swing Control for Faster Clock Signals

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Solution Overview

Problem

As the operating frequency of computer systems increases, semiconductor apparatuses face challenges in processing high-frequency signals due to decreasing signal amplitudes, which affects the operational speed and reliability of buffer circuits used in these systems.

Innovation Solution

A buffer circuit design that includes a driving control circuit and a driving circuit, capable of adjusting voltage levels and generating pull-up and pull-down control signals within specific swing ranges to improve signal processing and response speed, utilizing MOS transistors and voltage fixing and adjusting circuits to optimize signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the operating frequency of computer systems is increased, then the processing speed and operational performance are improved, but the signal amplitude decreases which affects the reliability and operational speed of buffer circuits

Engineering Contradiction:
Improveoperating frequencyVSAvoidsignal amplitude
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies parameter changes by adjusting the voltage levels of control signals within specific swing ranges. The driving control circuit generates pull-up and pull-down control signals with optimized voltage levels that adapt to high-frequency operation, maintaining sufficient signal amplitude despite increased operating frequency. This resolves the contradiction by dynamically adjusting electrical parameters to preserve reliability while enabling higher speed operation.

Inventive Principle:
Principle #35Parameter changes

2Speed

If the voltage level swing range of control signals is reduced, then the response speed of the buffer circuit is improved, but the signal processing capability may be affected

Engineering Contradiction:
Improveresponse speedVSAvoidsignal processing capability
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent applies local quality by creating different voltage swing ranges for different control signals. The pull-up control signal operates within a first swing range while the pull-down control signal operates within a second swing range, allowing each signal to be optimized for its specific function. This enables the buffer circuit to achieve fast response speed through localized voltage optimization while maintaining overall signal processing capability through differentiated control strategies.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240356550A1Buffer circuit, clock generating circuit, semiconductor apparatus and semiconductor system using the same
Publication Date: 2024.10.24 SK HYNIX INC
  • US20240356550A1 patent drawing
  • US20240356550A1 patent drawing
  • US20240356550A1 patent drawing

AI summary

A buffer circuit includes a driving control circuit and a driving circuit. The driving control circuit changes a voltage level of an input signal to generate a pull-up control signal and a pull-down control signal. The pull-up control signal has a voltage level lower than a high boundary voltage level of the input signal. The pull-down control signal has a voltage level higher than a low boundary voltage level of the input signal. The driving circuit generates an output signal based on the pull-up control signal and the pull-down control signal.