Clock Skew Detection Circuit Using NAND and NOR Timing
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Solution Overview
Problem
As integrated circuit technologies scale, clock skew between global clock signals becomes a significant issue due to differences in clock signal paths, stray capacitance, and other factors, affecting synchronization and performance.
Innovation Solution
The implementation of detector circuitry that evaluates the skew between clock signals by generating signals indicating NAND and NOR combinations, using large transistors in combinatorial logic gates to mitigate jitter and distortion, and applying delays to compensate for skew through programmable delay lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If global clock frequency is increased to improve processing speed, then productivity increases, but clock skew between different locations on the chip worsens
Solution Approach 1:
The patent applies preliminary action by measuring clock skew before it critically affects operations. The detector circuitry continuously monitors skew between clock signals arriving at different locations, and the system adjusts timing parameters in advance to prevent synchronization failures, rather than reacting after problems occur.
Solution Approach 2:
The patent implements feedback through detector circuitry that continuously measures clock skew between different clock signals and feeds this information back to the clock distribution system. This feedback loop enables dynamic adjustment of clock timing to maintain synchronization despite varying skew conditions caused by different path lengths and capacitance values.
2Adaptability or versatility
If clock signal path length is increased to reach distant circuit components, then adaptability improves, but clock skew increases
Solution Approach 1:
The patent applies local quality by allowing different clock signal paths to have different characteristics (lengths, capacitances) tailored to their specific destinations. The detector circuitry measures skew locally at each destination point, and the system adjusts timing locally for each clock signal path rather than attempting uniform timing across the entire chip, accommodating variations in path length and load.
3Measurement precision
If detector circuitry is added to measure clock skew, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent applies universality by designing detector circuitry that can measure skew between any pair of clock signals regardless of their source or destination. The same detector circuit architecture can be reused throughout the chip to monitor multiple clock paths, reducing overall complexity compared to having dedicated measurement circuits for each specific clock pair.
Data Source
AI summary
Techniques and mechanisms for determining an amount of skew between two clock signals. In an embodiment, detector circuitry receives a first signal and a signal which indicate (respectively) a NAND combination of clock signals, and a NOR combination of the clock signals. The detector circuitry evaluates a first length of time that the first signal indicates a respective first logic state, and a second length of time that the second signal indicates a respective second logic state. The skew is calculated based on a difference between the first length of time and the second length of time. In another embodiment, one of the first signal or the second signal is generated with a combinatorial logic gate, a transistor of which is relatively large, as compared to another transistor which is to operate based on one of the first signal, the second signal, or the clock signals.