12T Memory Cell Low Voltage Operation via Segmented Transistors
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Solution Overview
Problem
Conventional SRAM memory cells, such as the 6T design, face challenges in operating effectively at low voltage levels due to write-ability and read-stability issues, and alternative designs may compromise on area consumption or manufacturability.
Innovation Solution
A 12T memory cell configuration incorporating a transmission gate, cross-coupled inverter circuit, and tri-state inverter, allowing for efficient read and write operations at lower voltages, with transistors in the read and write ports optimized for different threshold voltages to balance performance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a 6T memory cell design is used, then the area consumption is reduced, but the device cannot operate adequately at low voltage levels due to write-ability and read-stability issues
Solution Approach 1:
The memory cell is divided into multiple transistor components (12 transistors total) with specialized functions. The write port transistors are optimized for write operations while read port transistors are optimized for read operations, allowing each segment to be tuned for its specific function rather than requiring all transistors to be equally optimized for all operations.
Solution Approach 2:
Different threshold voltages are assigned to different transistor groups within the memory cell. Specifically, read port transistors have threshold voltages optimized for low-leakage operation during read modes, while write port transistors have threshold voltages optimized for write operations. This local differentiation allows the cell to achieve low voltage operation capability without excessive area overhead.
2Reliability
If alternative memory cell designs are used to achieve low voltage operation, then low voltage capability is improved, but area consumption increases or manufacturability becomes challenging
Solution Approach 1:
The memory cell employs dynamic threshold voltage optimization where transistors are selected and configured based on the operational mode. During read operations, transistors with lower threshold voltages are activated to minimize leakage current, while during write operations, transistors with appropriate threshold voltages for writeability are engaged. This dynamic adaptation allows low voltage operation without permanently increasing area.
Solution Approach 2:
The invention changes the threshold voltage parameter of different transistor groups to optimize performance. By carefully selecting threshold voltage values for read port versus write port transistors, the cell achieves low voltage operation capability. The parameter optimization is done at the transistor level, allowing fine-grained control over the cell's electrical characteristics without requiring large area increases.
3Ease of operation
If transistors are optimized for low threshold voltage to improve write ability, then write-ability is improved, but leakage current increases
Solution Approach 1:
The transistor group is segmented into write port transistors and read port transistors with different threshold voltage optimizations. Write port transistors use threshold voltages optimized for write ability, while read port transistors use threshold voltages optimized for low leakage during read operations. This segmentation allows the cell to achieve good write ability without suffering from excessive leakage current during standby or read modes.
Solution Approach 2:
Different threshold voltage characteristics are applied locally to different transistor subsets within the memory cell. The read port transistors have threshold voltages specifically optimized to minimize leakage current during read operations and standby modes, while write port transistors have threshold voltages optimized for writeability. This local quality differentiation resolves the contradiction between write ability and leakage current.
Data Source
AI summary
A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.