Digital Storage TRIZ Cases

Selective row hammer refresh operations based on bank activity reduce power consumption and processing overhead while maintaining data integrity.

A segmented reference trimming method calibrates independent current sources for memory array segments to align with local resistance distributions.

A semiconductor memory device uses an equalizer circuit to charge selected and adjacent unselected bit lines simultaneously for high-speed sensing.

A semiconductor storage device staggers write commands across multiple banks using a delay controller to manage power delivery.

Segmenting transistors into optimized read and write ports resolves low voltage operation capability issues while managing leakage current.

A write driving circuit drives global input output lines using test data signals in a dedicated test mode.

A memory circuit output buffer routes data through a dedicated interface to enable flexible calibration of timing parameters.

Floating the ground reference level for un-accessed rows reduces leakage current without impacting memory speed or static noise margin.

A valid strobe signal generation circuit filters internal strobe pulses to produce a clean signal for data latching.

A dual pre-read method detects misplaced threshold voltages in multi-level NAND flash memory cells before the second programming pass.

Body bias voltage control adjusts threshold offsets in sense amplifiers, eliminating capacitive delays that reduce bandwidth.

Output control circuit encodes symbols with inverted logic levels to prevent voltage swinging and maintain valid windows.

Asymmetric bit line configuration reduces parasitic capacitance on read data lines to enhance reading speed in semiconductor memory devices.

A strobe generator creates a data strobe signal using a phase-shifted clock to synchronize read timing with the memory array.

A resistive memory device uses tile-specific write drivers to deliver position-dependent currents for precise data storage operations.

A timing control circuit adjusts variable delay to align write data with internal clock signals in semiconductor memory devices.

Dynamic port assignment control swaps circuitry mappings between dual ports to optimize access timing and reduce wait states.

Segmented bias phases reduce power consumption and minimize disturbances to unselected memory cells during sensing operations.

Asymmetrical precharge elements compensate for capacitance mismatches between bit lines and bars, eliminating sacrifice memory arrays.

A refresh control circuit uses a variable delay unit and piled delay unit to generate sequential pulse signals.

Segmented pull-up and pull-down circuits accelerate voltage transitions in DRAM generators without degrading PSRR or stability.

Pull-up circuit clamps non-zero bit line to power rail voltage, increasing voltage difference to resolve unreliable write operations at smaller feature sizes.

Level shifters drive periphery supply signals to maintain synchronization while reducing current consumption.

A half-Vdd bitline precharge circuit reduces power dissipation in six-transistor static random access memory arrays.

A semiconductor memory device uses dummy cells to detect refresh characteristics and generate adaptive control signals for the refresh driving unit.

Dual offset voltage storage cells in a sense amplifier compensate for transistor mismatch, improving read accuracy.

A single-transistor DRAM structure uses a floating body to couple word line potential to the channel for reliable charge storage.

A magnetic memory device uses shared selection transistors to connect multiple memory elements, improving current driving performance.

Row control unit activates adjacent word lines to prevent coupling-induced data degradation without requiring separate refresh addresses.

A semiconductor memory driver uses a voltage adjuster to compensate for normal drive levels.

A semiconductor memory device detects the latest rising output signal from replica circuits to determine optimal sense amplifier activation timing.

An access line bias circuit correlates reference and clamp currents to stabilize read margins in memory arrays.

Transmitting supply voltage through a word line reduces electrical leakage in memory circuits by enabling periodic activation during write operations.

A semiconductor memory device outputs received command signals back to the controller for verification.

A memory system applies varying delays to control signals across different arrays based on their proximity to input and output terminals.

A semiconductor integrated circuit device uses a multiplexer unit to route test data from multiple global lines for simultaneous memory chip evaluation.

A write driving unit generates single or multiple voltages for phase change memory cells based on stored data states.

Multiple data register buffers segment memory chips to shorten interconnect lines and reduce electrical load on motherboard traces.

A virtual array and differential amplifier circuit determine VCMA MRAM storage states by comparing matched memory cells, resolving resistance deviation risks.

A semiconductor memory apparatus generates synchronized signals internally to convert serial data into parallel format for storage.

AC signal modulation measures capacitance differences to eliminate charge amplifiers, enabling cost-effective wireless reading of ferroelectric memories.

A resistive memory operating method applies set and reset cycles to restore electrical conductivity parameters after thermal conditioning steps.

A two-stage guardband method tests SRAM cells to identify stable memory units resistant to random telegraph noise.

A hybrid computing-in-memory structure uses digital and analog local cells to generate output values.

Digital temperature sensors generate compensation signals that maintain sense amplifier decision edges across varying thermal conditions.

Unifies DQS0 and DQS1 delay adjustments to resolve signal skew, reducing controller complexity and power consumption.

A memory bus architecture multiplexes address and control information onto data signals to reduce required pin count.