Bit Line Equalizing Circuit Asymmetrical Precharge
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Solution Overview
Problem
In semiconductor memory apparatuses with open bit-line structures, achieving accurate capacitance matching between bit lines and bit line bars is challenging, leading to increased operation time due to capacitance mismatches, which results in longer RAS precharge times and potential decreases in net die area.
Innovation Solution
A bit line equalizing circuit with a pair of precharge elements having an asymmetrical contact resistance ratio is used, ensuring that both bit lines reach the precharge voltage level simultaneously by controlling the resistance values and contact lengths, eliminating the need for sacrifice memory cell arrays and improving capacitance matching precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sacrifice memory cell arrays are disposed at both edges of the bank to enable sensing operation, then bit line capacitance matching is achieved, but net die area is reduced
Solution Approach 1:
The patent extracts the capacitance matching function from the sacrifice memory cell arrays and implements it using dedicated capacitance matching circuits. This separates the sensing function from the capacitance matching function, allowing the sacrifice cell arrays to be removed or reduced while maintaining accurate capacitance matching through the dedicated circuits.
Solution Approach 2:
The patent introduces capacitance matching circuits as intermediary components between the bit line sense amplifiers and the bit lines. These intermediary circuits provide the necessary capacitance matching without requiring additional sacrifice memory cell arrays, thus preventing net die area reduction while maintaining manufacturing precision.
2Device complexity
If precharge elements with symmetrical contact resistance are used, then circuit design is simplified, but bit lines reach precharge voltage at different times due to capacitance mismatch
Solution Approach 1:
The patent applies asymmetry by configuring precharge elements with different contact resistance values on each side of the bit line sense amplifier. This asymmetric design compensates for the capacitance differences between bit lines and bit line bars, ensuring that both reach the precharge voltage level simultaneously, thereby optimizing the RAS precharge time.
Solution Approach 2:
The patent changes the resistance parameter of the precharge elements to achieve optimal performance. By adjusting the contact resistance values of the precharge elements based on the specific capacitance characteristics of the bit lines, the system achieves balanced precharging without requiring symmetrical design, thus reducing precharge time while maintaining design feasibility.
3Productivity
If bit line capacitance matching is not achieved accurately, then operation time increases, but using traditional methods reduces net die area
Solution Approach 1:
The patent replaces the mechanical approach of using physical sacrifice memory cell arrays for capacitance matching with an electrical circuit approach using dedicated capacitance matching circuits. This substitution achieves accurate capacitance matching for faster operation without the area penalty of additional memory cell arrays.
Data Source
AI summary
A semiconductor memory apparatus comprises bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio.