Refresh Control Circuit Area Reduction via Piled Delay
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Solution Overview
Problem
Conventional semiconductor apparatus refresh control circuits require a significant increase in circuit area to support operations beyond the 4 piled operation, due to the need for multiple variable delay units, which limits the layout margin.
Innovation Solution
A refresh control circuit design that includes a variable delay unit to generate a preliminary pulse signal from the quickest row address strobe signal and a piled delay unit to generate refresh period pulse signals, allowing for reduced circuit area by utilizing fewer delay units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple variable delay units are used to support piled operations beyond 4 piled operation, then the refresh control functionality is improved, but the circuit area increases significantly
Solution Approach 1:
The patent implements a universal refresh control circuit that can support multiple piled operation modes (4 piled, 8 piled, etc.) using a fixed number of variable delay units. The circuit achieves multi-functionality by dynamically configuring the existing delay units based on the operating mode, allowing a single circuit design to adapt to different piled operation requirements without proportionally increasing circuit area.
Solution Approach 2:
The patent merges the functionality of multiple variable delay units into a reduced set of delay units that can be dynamically configured. By combining the delay functions and sharing resources between what would traditionally require separate units, the circuit achieves the same piled operation support with fewer physical components, thereby reducing overall circuit area.
2Adaptability or versatility
If eight variable delay units are used to support 8 piled operation, then the piled operation capability is improved, but the layout margin is significantly reduced
Solution Approach 1:
The refresh control circuit is designed as a universal architecture that can support both 4 piled and 8 piled operations using the same set of delay units. By implementing mode-select logic that configures the delay units appropriately for each operation type, the circuit achieves 8 piled capability without requiring eight separate variable delay units, thus preserving layout margin.
3Adaptability or versatility
If four variable delay units are used for 4 piled operation, then the refresh control is improved, but the circuit area increases compared to simpler operations
Solution Approach 1:
The patent employs dynamic configuration of delay units based on the selected piled operation mode. The circuit uses control signals to dynamically adjust the timing and configuration of the variable delay units, allowing the same physical hardware to adapt its behavior for 4 piled, 8 piled, or other operation modes, optimizing the balance between functionality and circuit area.
Data Source
AI summary
A refresh control circuit of a semiconductor apparatus includes a variable delay unit configured to delay a signal that is activated quickest among a plurality of row address strobe signals activated at a predetermined time interval by a predetermined time, and to generate a preliminary pulse signal, and a piled delay unit configured to delay the preliminary pulse signal by various times, and to generate a plurality of refresh period pulse signals that are sequentially activated.