Single-Transistor DRAM Floating Body Coupling
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Solution Overview
Problem
DRAM memory cells without a capacitor face significant challenges due to strong capacitive coupling between the word line and the floating body, leading to noise interference, incorrect reading, and unintentional rewriting of data, making it difficult to implement such cells in practical applications.
Innovation Solution
A memory device using a semiconductor device is designed with a specific structure that includes multiple impurity layers and gate conductor layers, allowing for controlled voltage applications to manage carrier concentrations and electrical contact areas, thereby performing write and erase operations without the need for capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single transistor DRAM without a capacitor is used to achieve high integration density, then the integration density is improved, but noise interference from capacitive coupling between word line and floating body increases, causing incorrect reading and unintentional rewriting
Solution Approach 1:
The patent introduces a floating body as an intermediary element between the word line and the channel. This floating body acts as a mediator that couples the word line potential to the channel, enabling the single-transistor structure to function reliably. The floating body is formed by depositing a conductive layer on the semiconductor substrate in the channel region, creating a controlled coupling mechanism that allows the transistor to store and retrieve charges without requiring an external capacitor.
Solution Approach 2:
The patent modifies the electrical parameters of the transistor structure by controlling the potential of the floating body through word line voltage applications. By changing the voltage parameter applied to the word line, the potential of the floating body is adjusted, which in turn controls the charge storage and retrieval operations. This parameter control enables the system to achieve both high integration density and reliable data storage by managing the capacitive coupling effects.
2Speed
If impact ionization is used to generate carriers for write operations, then the write speed is improved, but unwanted carrier generation and noise increase occur
Solution Approach 1:
The patent applies local quality by creating a highly doped region (first impurity layer) at the interface between the semiconductor layer and the floating body. This localized doping concentration creates a region with different electrical properties that facilitates controlled carrier generation through impact ionization during write operations, while minimizing unwanted carrier generation in other regions. The local quality change allows selective enhancement of write speed in the critical channel region.
Solution Approach 2:
The patent performs preliminary action by pre-forming the floating body structure and the first impurity layer before the write operation. This preliminary preparation ensures that the carrier generation pathway is already established and optimized, allowing impact ionization to occur efficiently and controllably during the write operation without generating unwanted carriers. The floating body is pre-positioned to receive and store the generated carriers effectively.
3Speed
If the floating body is strongly coupled to the word line for fast charge storage, then the write speed is improved, but voltage margin is reduced and substrate depletion effects become notable
Solution Approach 1:
The patent applies dynamics by making the coupling between the word line and the floating body controllable and adjustable. The coupling strength can be dynamically changed by controlling the word line voltage potential. During write operations, strong coupling enables fast charge storage, while during read operations or when voltage margin is critical, the coupling can be weakened by adjusting the word line potential. This dynamic control allows the system to optimize between speed and voltage margin based on operational requirements.
Solution Approach 2:
The patent segments the electrical structure by introducing the floating body as a separate, controllable element between the word line and the channel. This segmentation allows independent control of the coupling strength between the word line and the channel region. The floating body acts as an intermediate stage that can be independently biased, enabling the system to achieve fast charge storage when needed while maintaining voltage margin when required, thus resolving the contradiction between speed and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise interference and improves data integrity, enabling the practical use of single-transistor DRAM cells by increasing the retention time of stored data and widening the voltage margin for memory operations.
Implementation Method 1
generating a group of electrons and a group of holes in the second semiconductor layer and the second impurity layer by using impact ionization that is caused by a current supplied between the third impurity layer and the fourth impurity layer
Implementation Method 2
generating a group of electrons and a group of holes in the second semiconductor layer and the second impurity layer by using impact ionization that is caused by a current supplied between the third impurity layer and the fourth impurity layer or by using a gate-induced drain leakage current
Data Source
AI summary
First and second impurity layers are formed on a first semiconductor layer on a substrate. A third gate insulating layer covers side walls of the impurity layers and the first semiconductor layer. First and second gate conductor layers and a second insulating layer are formed in a groove, and n+-layers connected to source and bit lines are formed at ends of a second semiconductor layer formed on the second impurity layer and covered with a second gate insulating layer, on which a third gate conductor layer connected to a word line is formed. An operation of maintaining holes generated in a channel region of the second semiconductor layer by impact ionization or a GIDL current near the gate insulating layer and an operation of discharging the holes from the channel region are performed by controlling voltages applied to the source, bit, and word lines and first and second plate lines.