Memory Array Control Signal Delay Optimization
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Solution Overview
Problem
As memory devices increase in size, the lack of uniformity in semiconductor storage cells and access delays leads to pessimistic timing margins, resulting in inefficient data access and potential failures, especially in larger memory banks formed of individual arrays.
Innovation Solution
The memory system introduces varying delays to control signals across different arrays based on their proximity to the input and output, providing additional delay to arrays closer to the input and output, thereby increasing the safety margin for data detection without affecting overall access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform delay time is applied to all memory arrays to cover worst-case scenarios, then reliability is improved, but access time increases and productivity deteriorates
Solution Approach 1:
The patent applies different delay times to different memory arrays based on their specific characteristics. Arrays closer to the input/output are given longer delays, while arrays farther away receive shorter delays. This localized adjustment ensures each array receives appropriate timing without uniformly increasing overall access time, thus maintaining productivity while improving reliability for each specific array.
Solution Approach 2:
The patent changes the delay time parameter dynamically based on array location and characteristics. Instead of using a single fixed delay value for all arrays, the system adjusts the delay parameter locally for each array, optimizing the balance between reliable detection and fast access for different parts of the memory structure.
2Quantity of substance
If memory size is increased to provide greater storage capacity, then quantity of data storage is improved, but lack of uniformity in storage cells increases and reliability deteriorates
Solution Approach 1:
The patent divides the large memory into multiple separate arrays or banks. Each array can be independently accessed and timed. This segmentation allows the system to manage the increased variety of cell characteristics by treating each array as a separate unit with its own optimized delay parameters, maintaining reliability even as overall memory capacity increases.
Solution Approach 2:
The patent applies location-specific delay adjustments to different arrays within the larger memory structure. Arrays experiencing greater timing variations due to their position or cell characteristics receive customized delay values, compensating for the increased non-uniformity that arises in larger memory devices.
3Reliability
If delay time is increased to ensure worst-case sense amplifier triggering, then reliability is improved, but access time increases and productivity deteriorates
Solution Approach 1:
The patent applies delay adjustments specifically at the array level rather than uniformly across the entire memory. Arrays that require additional time for reliable sense amplifier triggering receive localized delay increments, while other arrays maintain their original faster timing. This ensures reliability where needed without unnecessarily extending overall access time.
Solution Approach 2:
The patent applies delay only where necessary - specifically to arrays that benefit from additional timing margin. Rather than adding delay universally, the system applies partial delay adjustments to specific arrays, avoiding excessive action that would unnecessarily slow down the entire memory system.
Data Source
AI summary
A memory is disclosed that comprises: an input for receiving an input signal and an output for outputting data; a plurality of data storage cells for storing individual units of data; said plurality of data storage cells being arranged in an array; a plurality of said arrays; each of said arrays comprising detecting circuitry for detecting and outputting stored data in response to a control signal received at said detecting circuitry; delay circuitry for providing a delay to said control signal sent to said detecting circuitry of at least some of said plurality of arrays, said delay provided to said control signal being longer for at least one array located closer to an input and output of said memory than it is to at least one array located further from an input and output of said memory.