Write Driving Circuit Test Mode for Memory Burn-In
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Solution Overview
Problem
Conventional write driving circuits for semiconductor memory devices face limitations in performing burn-in tests on multiple chips simultaneously due to the finite number of data input and output terminals, making it difficult to efficiently test and identify defective memory cells.
Innovation Solution
A write driving circuit that operates in a test mode, using a combination of first and second test data signals to drive global input/output lines, allowing data to be written to memory cells without relying on input data signals, thereby enabling simultaneous testing of multiple chips and reducing the need for data input pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional write driving circuits use data input pins to drive GIO lines, then normal write operations can be performed, but the number of required data pins increases and testing efficiency decreases
Solution Approach 1:
The patent changes the operational mode of the write driver by introducing a test mode that operates differently from normal mode. In test mode, the write driver responds to test data signals (TDATA0, TDATA1) and test mode signal (TMWTALL) without requiring input data signals, thereby reducing pin requirements and improving testing efficiency
Solution Approach 2:
The write driver is designed to perform multiple functions: normal write operations using input data signals and DINEV signals, and test operations using test data signals and test mode signals. This multi-functionality allows the same circuit to handle both normal operation and testing without additional dedicated test circuits
2Ease of operation
If the input buffer is enabled during test mode, then input data signals can be processed, but current consumption increases and test simplicity decreases
Solution Approach 1:
The input buffer's operational state is dynamically controlled based on the test mode signal. The input buffer controller responds to TMWTALL to disable the input buffer during test mode, reducing current consumption and simplifying the test input requirements
Solution Approach 2:
During test mode, the input buffer is extracted from the active signal path by disabling it. The test data signals bypass the input buffer and go directly to the write driver, eliminating the need for buffer operation and associated current consumption
Data Source
AI summary
A write driving circuit is provided to drive a global input/output line to write same data to memory cells according to a combination of a first test data signal and a second test data signal in a test mode, regardless of input data signals.