Low-pincount Memory Bus Multiplexing Address and Data Signals
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Solution Overview
Problem
Existing memory bus architectures require a large number of signals to connect memory ICs to controller ICs, leading to inefficiencies such as reduced average bus bandwidth and increased cost due to underutilized resources, especially in applications with primarily sequential memory access patterns.
Innovation Solution
A memory bus architecture that multiplexes address and control information onto data signals, reducing the number of required bus signals and enabling simultaneous data and command transfer, thereby improving bandwidth and reducing power consumption and IC size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of bus signals are used to connect memory ICs to controller ICs, then all memory functions can be supported, but the average bus bandwidth is reduced and cost increases due to underutilized resources
Solution Approach 1:
The patent combines address signals and data signals onto the same physical bus conductors by using time-division multiplexing. Address information is transmitted during a first time period when no data is being transferred, and data is transmitted during a second time period. This merging of address and data channels onto shared conductors reduces the total number of signals required while maintaining full memory functionality.
Solution Approach 2:
The patent implements periodic transmission of address and data signals by alternating between address transfer cycles and data transfer cycles. The bus operates in periodic phases where address information is presented to the memory device during activation periods, followed by data transfer periods. This periodic action allows the same physical resources to be reused for different functions at different times, improving bandwidth utilization.
2Adaptability or versatility
If a large number of bus signals are used to connect memory ICs to controller ICs, then all memory functions can be supported, but cost increases due to underutilized resources
Solution Approach 1:
The patent merges address and data signal paths by using the same physical bus conductors for both purposes. Instead of having separate dedicated conductors for address signals and data signals, the system uses time-division multiplexing to share the conductors, thereby reducing the total signal count and simplifying the bus interface architecture.
Solution Approach 2:
The bus conductors are designed to serve multiple functions: they can transmit address information during activation periods and data information during transfer periods. This multi-functionality allows the same physical resources to handle different types of information, reducing the need for dedicated specialized conductors and lowering overall system complexity.
3Adaptability or versatility
If separate resources for strobing, selecting and addressing memory ICs are used, then a high level of generality in applications is achieved, but many signals are underutilized adding cost with little marginal benefit
Solution Approach 1:
The patent combines multiple control functions (strobing, selecting, and addressing) into a unified time-division multiplexed signal structure. The same bus conductors that carry data also carry address and control information at different times, eliminating the need for separate dedicated control signal lines and reducing overall signal complexity while maintaining application versatility.
Solution Approach 2:
The bus system maintains continuous useful action by eliminating idle periods where control signals would be underutilized. During data transfer periods, the bus is fully utilized for data movement, and during activation periods, the same bus resources are used for address transmission rather than leaving control lines idle. This continuous utilization maximizes the effectiveness of each signal.
Data Source
AI summary
A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.