Valid Strobe Signal Generation Circuit for DDR Memory
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Solution Overview
Problem
DDR synchronous memory devices face errors during data latching due to internal strobe signal toggling during the preamble duration, which can lead to abnormal operations when detecting the final falling edge of the data strobe signal.
Innovation Solution
A data input circuit is designed with a valid strobe signal generation circuit to remove pulses from the internal strobe signal during the preamble period, generating a valid strobe signal that includes a data strobe signal counter to align data accurately at the time of a write operation, ensuring synchronization with the final falling edge of the data strobe signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the data strobe signal is set to high-Z or logic high level before preamble, then the circuit can operate in DDR mode, but internal strobe signal may be toggled during preamble causing errors
Solution Approach 1:
The patent applies preliminary action by generating a preamble detection signal before the actual data transfer to detect and ignore spurious strobe pulses that occur during the preamble period. The valid strobe signal generation circuit is activated in advance to filter out premature pulses, ensuring that only valid data strobe pulses are processed for data latching operations.
2Device complexity
If the internal strobe signal is used directly for data latching, then the circuit structure is simple, but data latching errors occur due to premature pulses during preamble
Solution Approach 1:
The patent introduces an intermediary valid strobe signal generation circuit that sits between the internal strobe signal and the data latching circuit. This intermediary circuit generates a cleaned-up version of the strobe signal by removing premature pulses during the preamble period, thus preventing latching errors without significantly complicating the overall system architecture.
3Difficulty of detecting and measuring
If the final falling edge detection is performed without preamble filtering, then the detection process is straightforward, but abnormal operations occur due to premature pulse toggling
Solution Approach 1:
The patent applies preliminary action by establishing a preamble detection mechanism that identifies and excludes spurious pulses before the final falling edge detection is performed. The valid strobe signal generation circuit prepares the signal in advance by filtering out premature toggles, ensuring that the falling edge detection operates on a clean, reliable signal waveform.
Data Source
AI summary
A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation.