Semiconductor Memory Testing via Parallel MUX Control
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Solution Overview
Problem
Highly integrated semiconductor memory devices face increased testing time and costs due to the need to individually test each memory cell, which can lead to reliability issues if failed cells are not precisely identified.
Innovation Solution
A semiconductor device and system design that includes a MUX unit, selection unit, and control unit to classify and output test data from multiple global lines, allowing for simultaneous testing of multiple memory chips by activating specific control buffers and output enable signals in a test mode, reducing the time required for memory cell testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells integrated into one memory chip is increased to achieve high integration, then the manufacturing capability and storage capacity are improved, but the possibility of failed memory cells increases and testing becomes more time-consuming
Solution Approach 1:
The patent segments the memory chip into multiple circuit blocks, each with its own MUX unit and control buffer. This segmentation allows parallel testing of different regions, reducing overall testing time while maintaining comprehensive coverage of all memory cells in high-density chips.
Solution Approach 2:
The patent changes the operational parameters by introducing test mode signals that alter the behavior of MUX units and control buffers. During test mode, these components operate differently to enable parallel test data output, transforming the testing process from sequential to parallel operation and significantly reducing testing time for high-integration chips.
2Reliability
If individual memory cells are tested to ensure reliability, then the quality and reliability are improved, but the testing cost and time increase significantly
Solution Approach 1:
The patent merges multiple test data outputs from different circuit blocks through a coordinated control mechanism. By combining parallel test operations across multiple circuit blocks with unified control, the system achieves comprehensive reliability testing without the time penalty of sequential individual cell testing.
Solution Approach 2:
The control buffer automatically selects and outputs test data from the appropriate MUX units based on test mode signals, enabling self-managed parallel testing across circuit blocks. This self-service mechanism reduces the need for complex external testing equipment and reduces testing time while maintaining reliability.
3Reliability
If comprehensive memory cell testing is performed to identify failed cells, then the reliability is improved, but the device complexity and testing cost increase
Solution Approach 1:
The MUX units and control buffers are designed with multi-functionality, serving both normal data output operations and test mode operations. This universality allows comprehensive reliability testing without adding dedicated complex test equipment, as the existing circuitry is repurposed for testing functions.
Solution Approach 2:
The system dynamically switches between normal mode and test mode through control signals. The MUX units and control buffers adapt their behavior based on the operational mode, enabling comprehensive testing functionality to be activated only when needed, thus avoiding permanent complexity increases while maintaining reliability.
Data Source
AI summary
A semiconductor integrated circuit device includes a first circuit block configured to receive data from a plurality of data I/O (input/output) lines and output test data in a test mode, and a second circuit block configured to connect the plurality of data I/O lines and the first circuit block, output the data of the plurality of data I/O lines in a normal mode and output the test data provided from the first circuit block in the test mode.