Semiconductor Memory Sensing Circuit with Segmented Bias Phases
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Solution Overview
Problem
Conventional techniques for sensing semiconductor memory devices often result in high power consumption and inaccurate data state determination due to large voltage swings and charge pumping effects, which can disturb unselected memory cells and reduce the net quantity of majority charge carriers in the electrically floating body region.
Innovation Solution
The implementation of a semiconductor memory device with a data sense amplifier circuitry and latch circuitry that includes a cross-coupled configuration of transistors to amplify voltage or current differences, a pre-charge circuitry, and input/output circuitry to accurately determine the data state stored in memory cells by managing bit line voltages and currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional reading techniques are used to sense memory cells by applying bias signals to source/drain regions and gate, then data state can be determined through current sensing, but power consumption increases and voltage swings cause disturbance to unselected memory cells
Solution Approach 1:
The sensing operation is divided into multiple phases: a first sensing phase that senses a first data state with first bias signals, and a second sensing phase that senses a second data state with second bias signals. This segmentation allows the device to accumulate sensing results from multiple phases, improving measurement precision while distributing power consumption across different phases rather than requiring high power in a single phase.
Solution Approach 2:
The sensing operation uses periodic application of bias signals across multiple sensing phases. By periodically applying and removing bias signals in a controlled sequence, the system can sense data states while minimizing continuous power consumption and reducing voltage swing disturbances to unselected cells through controlled timing.
2Adaptability or versatility
If pulsing between positive and negative gate biases is applied during read and write operations, then data state can be written to the memory cell, but the net quantity of majority charge carriers in the electrically floating body region is reduced, resulting in inaccurate data state determination
Solution Approach 1:
A compensation operation is performed before the sensing operation to compensate for charge carrier loss. This preliminary action restores the net quantity of majority charge carriers in the electrically floating body region by applying compensation bias signals, ensuring that the subsequent sensing operation can accurately determine the data state without being affected by previous write-induced carrier depletion.
Solution Approach 2:
The system uses feedback from the sensing operation results to control the compensation operation. Based on the sensed data state and the known effects of write operations, the system applies appropriate compensation bias signals to restore charge carrier levels, creating a feedback loop that maintains measurement precision while preserving writing capability.
3Measurement precision
If bias signals are applied to read memory cells, then data state can be sensed through current measurement, but voltage swings disturb unselected memory cells and reduce sensing accuracy
Solution Approach 1:
The sensing operation is segmented into multiple phases with different bias signal configurations. By sensing the same data state multiple times under different bias conditions and combining the results, the system improves measurement precision while reducing the impact of voltage swing disturbances on unselected cells, as not all cells are equally affected in each phase.
Data Source
AI summary
Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor.