Word Line Supply Voltage Memory Circuit Leakage Reduction
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Solution Overview
Problem
Memory circuits face significant electrical leakage due to continuous activation and deactivation of logic circuits, particularly through transistors coupled to a continuous power supply, which existing solutions fail to adequately address without increasing manufacturing complexity or reducing leakage effectively.
Innovation Solution
A memory circuit structure that uses a word line to transmit a supply voltage to a transistor array, allowing for efficient writing of bits to memory elements while minimizing leakage by using a transistor array with specific doping types and configurations to control current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If transistors with higher threshold voltages and more robust logic configurations are implemented to reduce electrical leakage, then leakage is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies periodic action by using pulsed word lines that are activated only during specific write operations rather than continuous activation. The word line receives a supply voltage pulse only when data needs to be written to the memory cell, and remains inactive otherwise. This periodic activation pattern significantly reduces electrical leakage through the transistor while maintaining the ability to perform write operations when needed, without requiring higher threshold voltage transistors or more complex logic configurations.
2Reliability
If continuous power supply is provided to logic circuits for continuous operation, then operational reliability is improved, but electrical leakage increases
Solution Approach 1:
The patent applies dynamics by making the power supply to the logic circuit dynamic rather than static. The word line is connected to a supply voltage that can be dynamically enabled or disabled based on operational needs. During write operations, the word line is activated with supply voltage to ensure reliable operation. During non-operational periods, the supply voltage is disabled, eliminating leakage current while maintaining the capability for reliable operation when needed.
3Loss of energy
If more robust logic configurations are used to reduce leakage, then leakage is reduced, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the operational parameters of the existing logic circuit rather than changing its structural complexity. Specifically, the supply voltage parameter is changed from continuous to pulsed/intermittent based on write operation requirements. This parameter modification reduces leakage current significantly while maintaining the same simple logic configuration, avoiding the need for more complex circuit designs.
Data Source
AI summary
Embodiments of the present disclosure provide a memory circuit structure including a transistor array for writing a plurality of bits to a memory element. The transistor array includes a first transistor having a first source/drain terminal for receiving a supply voltage. A first word line is coupled between a decoder and the first source/drain terminal of the first transistor. The first word line transmits a voltage output from the decoder to the first transistor as the supply voltage.