Row-Based Memory Read Write Support Circuitry Leakage Reduction
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Solution Overview
Problem
Existing memory technologies face challenges in reducing leakage current, particularly as the number of ports increases, which affects power consumption and memory speed, and existing solutions either compromise memory speed or increase access time.
Innovation Solution
The proposed solution involves floating the ground reference level for un-accessed rows during read and write operations, using transistors and diodes to create current paths that reduce leakage current without affecting the content of the bit cell or changing the static noise margin, thereby reducing leakage current on a per-row basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the ground reference level is raised and/or operational supply voltage is lowered at the memory array level to reduce leakage current, then leakage current is reduced, but power consumption and speed are affected
Solution Approach 1:
The memory array is divided into multiple segments, with each segment having independent voltage control. This allows selective voltage adjustment in active segments while maintaining optimal voltage in inactive segments, reducing leakage without compromising overall memory speed
Solution Approach 2:
Different voltage levels are applied to different segments of the memory array based on their operational state. Active segments receive full supply voltage for high-speed operation, while inactive segments have reduced voltage to minimize leakage current
2Loss of energy
If the bit line is floated during retention period to reduce leakage current, then leakage current is reduced, but memory access time increases due to the need to raise the bit line back to voltage VDD
Solution Approach 1:
The bit line is pre-charged to voltage VDD before the read operation begins. This preliminary action eliminates the need to raise the bit line voltage during the access period, reducing memory access time while maintaining low leakage during retention through proper timing of the float operation
3Loss of energy
If high threshold voltage (HVT) bit cells are used to reduce leakage current, then leakage current is reduced, but memory access time increases
Solution Approach 1:
The threshold voltage of bit cells is dynamically adjusted based on operational mode. During active read/write operations, lower threshold voltage transistors are used for fast access. During retention periods, the threshold voltage is increased to reduce leakage current, achieving both low leakage and fast access without compromise
Data Source
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AI summary
A circuit comprises a plurality of memory cells (110) in a row, at least one write word line (WWL), and a write support circuit (120) coupled to the at least one write word line and to the plurality of memory cells in the row. The write support circuit includes a first current path (transistor N7 of 120) and at least one second current path (diode D of 120). A current path of the at least one second current path corresponds to a respective write word line of the at least one write word line. A write word line of the at least one write word line is configured to select the first current path when the plurality of memory cells in the row operates in a first mode, and to select a second current path of the at least one second current path when the plurality of memory cells in the row operates in a second mode.