Sense Amplifier Offset Compensation via Dual Storage Cells
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Solution Overview
Problem
The performance of semiconductor memory is adversely affected by transistor mismatch in sense amplifiers, leading to misalignment voltage issues that impact data reading accuracy.
Innovation Solution
A sense amplifier design incorporating a first and second offset voltage storage cell, where the offset voltage is stored in one cell when data is read from the first bit line and in the other cell when data is read from the second bit line, using a configuration of PMOS and NMOS transistors and switches to manage voltage differences and compensate for transistor misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of semiconductor memory is reduced, then memory density is improved, but transistor mismatch increases causing larger misalignment voltage
Solution Approach 1:
The patent divides the offset compensation mechanism into two separate offset voltage storage cells (first and second offset voltage storage cells), each dedicated to storing offset voltages for specific bit lines. This segmentation allows independent compensation for each bit line, addressing the transistor mismatch problem that worsens with reduced memory size by providing targeted offset storage rather than a shared mechanism.
2Device complexity
If offset voltage is stored in a single storage cell, then device complexity is reduced, but read accuracy deteriorates due to inability to compensate for bit line specific misalignment
Solution Approach 1:
The patent implements separate offset voltage storage cells for different bit lines (first offset voltage storage cell for first bit line, second offset voltage storage cell for second bit line). This segmentation enables each storage cell to hold bit line specific offset voltages, improving read accuracy by providing targeted compensation while maintaining relatively simple circuit implementation.
Solution Approach 2:
The patent applies local quality by dedicating specific offset voltage storage cells to specific bit lines. Each storage cell is optimized to store offset voltages relevant to its associated bit line, providing localized compensation that improves read accuracy for each bit line independently rather than using a generic shared storage mechanism.
Data Source
AI summary
A sense amplifier includes: an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit, wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell.