Memory Read Timing via Phase-Shifted Strobe Signal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multiple data rate memory systems face challenges in providing reliable timing for data read operations, particularly due to the sensitivity of DQS circuitry to temperature, voltage, and process variations, which can lead to reliability issues and increased complexity.
Innovation Solution
A memory system that uses phase shift clock signals to generate a data strobe signal with a precise 90-degree phase shift relative to the master clock, allowing for simpler and more reliable read timing by transmitting the data with a delayed strobe signal that is synchronized with the clock, thereby reducing the complexity of the delay circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional DQS circuitry is used to provide timing for data read operations, then data can be read at double data rate, but the circuitry becomes sensitive to temperature, voltage, and process variations leading to reliability problems
Solution Approach 1:
Instead of delaying the DQS signal in the controller (traditional approach), the patent inverts the approach by generating the DQS signal in the memory device itself using a phase-shifted clock. This transfers the timing function from the controller to the memory, eliminating the need for complex delay circuitry in the controller and reducing sensitivity to environmental variations.
Solution Approach 2:
The patent introduces a phase-shifted clock signal as an intermediary mechanism. This clock signal, shifted by a specific phase angle (e.g., 45 degrees), serves as a stable reference for generating the DQS signal, providing a more reliable timing source compared to traditional delay-based approaches.
2Measurement precision
If complex DQS delay circuitry is designed to achieve effective reading, then data timing can be controlled, but the circuit requires much more space than expected
Solution Approach 1:
The patent extracts the DQS generation function from the controller and relocates it to the memory device. This removes the need for complex delay circuitry in the controller, significantly reducing the area required for timing control circuitry while maintaining precise timing control through the phase-shifted clock mechanism.
Solution Approach 2:
The patent uses a simplified copying approach where the phase-shifted clock signal directly generates the DQS signal in the memory device, eliminating the need for complex delay circuits. This reduces the area requirement while preserving timing precision.
3Ease of manufacture
If process improvement is made to enhance manufacturing, then production efficiency increases, but reliability problems are created for the DQS delay circuit
Solution Approach 1:
The memory device generates its own DQS signal using the phase-shifted clock, making the timing function self-contained within the memory device. This eliminates the external delay circuitry that is sensitive to process variations, allowing process improvements without compromising reliability.
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A memory (14 or 24) includes a memory array (18 or 26), read circuitry (20 or 28), and a strobe generator (22 or 30). The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees.