Magnetic Memory Shared Selection Transistor Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices, such as DRAMs and flash memory, face limitations in terms of volatility, speed, and power consumption, prompting the need for a memory technology that combines high stability, miniaturization, and efficient data storage.
Innovation Solution
A magnetic memory device with a cell array structure featuring word lines, bit lines, metal wiring patterns, and selection transistors, where multiple magnetic memory elements share a selection transistor, allowing for improved current driving performance and reduced size, enabling efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If each magnetic memory element is connected to a dedicated selection transistor, then the current driving performance is improved, but the device size increases and manufacturing complexity increases
Solution Approach 1:
Multiple magnetic memory elements share a common selection transistor instead of each element having a dedicated selection transistor. This merging approach reduces the total number of selection transistors in the array, thereby reducing device complexity and manufacturing difficulty while maintaining acceptable current driving performance through the shared structure.
Solution Approach 2:
The shared selection transistor serves multiple magnetic memory elements simultaneously, making it a multi-functional component. This universal approach allows a single selection transistor to control access to multiple memory elements, reducing overall device complexity while still enabling proper selection and current driving for individual elements when needed.
2Device complexity
If multiple magnetic memory elements share a selection transistor, then the device size is reduced, but the current driving performance may be compromised
Solution Approach 1:
The patent merges multiple memory elements under a single selection transistor control, reducing device size. The shared selection transistor is designed with sufficient current driving capability to serve multiple elements, balancing size reduction with maintained performance through proper transistor sizing and design.
Solution Approach 2:
The patent employs a three-dimensional stacked memory architecture where magnetic tunnel junctions are stacked vertically. This dimensional change allows multiple memory elements to share selection transistors in the vertical dimension while maintaining horizontal integration density, effectively reducing overall device footprint without compromising current driving performance through the shared transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The magnetic memory device achieves enhanced current driving performance and miniaturization, addressing the limitations of existing memory technologies by utilizing a shared selection transistor structure for improved data storage and retrieval efficiency.
Implementation Method 1
Magnetic memory devices use variations in the resistive state of a magnetic material that result from variations in the magnetization direction of the magnetic material
Data Source
AI summary
A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.