Multiport SRAM Port Assignment Control for Access Timing
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Solution Overview
Problem
Multi-port memory devices face challenges in coordinating simultaneous access requests from multiple resources, leading to unpredictable access times and compatibility issues with logic units operating at different frequencies.
Innovation Solution
The implementation of a dual-port memory system with asynchronous clocking (CLKX and CLKY) and port assignment control circuitry, allowing either X-circuitry or Y-circuitry to process access requests from ports A and B, with the ability to swap assignments based on access conditions to optimize access times without conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wait states and arbitration are used to coordinate multi-port access, then access to storage elements is enabled for multiple resources, but access times become unpredictable
Solution Approach 1:
The memory device is divided into separate circuitries (X-circuitry and Y-circuitry) that can independently process access requests from different ports. Each circuitry has its own word lines and bit line pairs, allowing simultaneous independent operations without arbitration delays.
Solution Approach 2:
The port assignment control circuitry dynamically switches between different port-to-circuitry mappings based on access conditions. The system can swap assignments between ports A/B and X/Y circuitries to optimize access timing, transforming static arbitration into dynamic scheduling that maintains predictability.
2Adaptability or versatility
If multiport memory interfaces to logic units with different operating frequencies, then connectivity is achieved, but coordination becomes complex
Solution Approach 1:
The memory device separates its internal operations into independent circuitries that can operate asynchronously. The X-circuitry and Y-circuitry are independently controlled by their own word lines and bit line pairs, allowing each to synchronize with different external logic units operating at different frequencies without creating coordination complexity.
Solution Approach 2:
The dynamic port assignment control allows the memory to adapt its internal timing based on external access patterns. By swapping circuitry assignments based on access conditions, the system can maintain simplified coordination with external logic units regardless of their operating frequencies.
3Productivity
If simultaneous read and write accesses are enabled, then productivity increases, but access conflicts may occur
Solution Approach 1:
The memory device uses separate word lines and bit line pairs for different circuitries, creating physically isolated access paths. This segmentation prevents conflicts between simultaneous read and write operations by ensuring that X-circuitry and Y-circuitry operate on disjoint sets of memory lines at any given time.
Solution Approach 2:
The port assignment control circuitry acts as an intermediary that manages and coordinates access requests before they reach the memory array. By dynamically assigning ports to circuitries and swapping assignments when necessary, it prevents access conflicts while enabling simultaneous operations.
Data Source
AI summary
A multiport SRAM has an array of cells, a first port, and a second port. During a period of different row addresses for the ports, the first port uses first word lines and first bit lines. The second port uses second word lines and second bit lines. In response to the second port switching to the same address as the first port to make a row match, the second port and the first port use the first plurality of word lines, but the first port uses the first plurality of bit lines and the second port uses the second plurality of bit lines. If the row match is removed by the first port changing row addresses, a correlation swap is performed so that the first port performs accesses using the second word lines and bit lines and the second port performs accesses using the first word lines and bit lines.