Semiconductor Memory Synchronized Signal Generation Circuit
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Solution Overview
Problem
Current semiconductor memory apparatuses require multiple channels and pins for data input/output operations, which can be inefficient and limit testing speed, especially when using external data input/output strobe signals and clocks.
Innovation Solution
A semiconductor memory apparatus that includes a synchronized signal generation circuit for producing data input/output strobe signals or delay locked clock signals, a serial-to-parallel data conversion unit, and a data storage region, allowing for efficient conversion and storage of data using internally generated synchronized signals, reducing the need for external signals and pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple channels and pins are used for data input/output operations with external strobe signals and clocks, then data transmission capability is improved, but pin utilization efficiency deteriorates and device complexity increases
Solution Approach 1:
The synchronized signal generation circuit is configured to output different types of synchronized signals (data input/output strobe signals in normal mode, delay locked clock signals in test mode) based on operation mode, allowing the same hardware circuit to serve multiple functions and reducing the need for separate dedicated circuits for different operation modes
2Speed
If external data input/output strobe signals are used for high-speed data input/output, then data transmission speed is improved, but the number of external pins required increases
Solution Approach 1:
The synchronized signal generation circuit generates the necessary synchronized signals internally using the delay locked clock signal as a reference, eliminating the need for external data input/output strobe signals and reducing pin requirements while maintaining high-speed data input/output capability
3Adaptability or versatility
If separate test mode circuits are added to support testing operations, then testing capability is improved, but device complexity increases
Solution Approach 1:
The synchronized signal generation circuit operates in multiple modes (normal operation mode and test mode) by changing its output signal type based on control signals, allowing the same hardware to support both normal data input/output operations and test operations without requiring separate dedicated circuits
Data Source
AI summary
A semiconductor memory apparatus includes a synchronized signal generation circuit, a serial-to-parallel data conversion unit and a data storage region. The synchronized signal generation unit outputs one of a data input/output strobe signal and a delay locked clock signal as synchronized signals in response to a control signal in a write operation. The serial-to-parallel data conversion unit converts serial data into parallel data in response to the synchronized signals. The parallel data is stored in the data storage region.