Row Hammer Refresh Control in Memory Banks
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Solution Overview
Problem
Memory devices experience data corruption due to the row hammer effect, where frequent access to a particular row leads to adverse effects on adjacent rows, causing intermittent failures and increased power consumption through unnecessary refresh operations.
Innovation Solution
The row hammer refresh rate of memory banks is independently adjusted based on the activity level of each bank, eliminating unnecessary refresh operations and reducing power consumption while maintaining performance and reliability by monitoring active signals and adjusting refresh rates accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If row hammer refresh operations are performed on all memory banks, then data corruption from row hammer effect is prevented, but power consumption increases due to unnecessary refresh operations on inactive banks
Solution Approach 1:
The patent applies local quality by performing row hammer refresh operations selectively on only those memory banks that have experienced row hammer activity, rather than uniformly refreshing all memory banks. The memory device monitors row access patterns per bank and triggers refresh operations only on affected banks, making the refresh behavior localized to the specific area needing protection.
Solution Approach 2:
The patent implements dynamics by making the refresh rate adaptive based on actual row hammer activity detected in each memory bank. The system dynamically adjusts refresh operations from a static uniform approach to a dynamic selective approach, where refresh intensity and frequency are modulated according to real-time monitoring of row access patterns and hammering events in each bank.
2Reliability
If row hammer refresh operations are performed frequently, then protection against data corruption is enhanced, but processing overhead and performance degradation increase
Solution Approach 1:
The patent applies partial action by performing refresh operations on only a subset of memory banks that are actually experiencing row hammer effects, rather than applying excessive refresh operations to all banks. This selective approach provides sufficient protection where needed while avoiding unnecessary processing overhead on inactive banks.
Solution Approach 2:
The patent implements feedback by continuously monitoring row access patterns and hammering events in each memory bank, then using this information to control when and where refresh operations are performed. The system measures row hammer activity and adjusts refresh behavior accordingly, creating a closed-loop control system that optimizes the balance between protection and performance.
3Device complexity
If uniform refresh rate is applied to all memory banks, then implementation simplicity is maintained, but energy efficiency decreases due to inability to adapt to varying activity levels
Solution Approach 1:
The patent applies segmentation by dividing the memory device into independent monitorable units at the memory bank level, where each bank can be monitored and refreshed independently based on its own activity patterns. This segmentation enables granular control of refresh operations, allowing the system to apply different refresh strategies to different banks rather than using a monolithic uniform approach.
Solution Approach 2:
The patent implements self-service by enabling each memory bank to effectively monitor its own row access patterns and trigger its own refresh operations based on detected hammering events. The memory device as a whole provides the monitoring and control infrastructure, but individual banks autonomously determine when they need refresh protection based on their own activity.
Data Source
AI summary
Memory devices are disclosed. A memory device may include a memory bank and circuitry configured to monitor a number of active commands received at the memory bank. The circuitry may also be configured to activate a refresh operation of the memory bank based on the number of active commands received at the memory bank. Methods and systems are also described.