Half-Vdd Bitline Precharge for Low-Power 6T SRAM
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Solution Overview
Problem
Conventional six-transistor static random access memory (6T SRAM) faces challenges in reducing power dissipation while maintaining stable read and write operations, particularly due to issues with bit-line power and read/write signal margins.
Innovation Solution
The implementation of a half-Vdd bitline precharge scheme and a two-step word line voltage approach for 6T SRAM, where the bitlines are precharged to Vdd/2 and the word line voltage is boosted during write operations, to optimize power consumption and signal margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full-Vdd bitline precharge scheme is used in conventional 6T SRAM, then read and write operations are stable, but power dissipation is high
Solution Approach 1:
The patent changes the bitline precharge voltage parameter from full-Vdd to Vdd/2, reducing the voltage swing and associated power dissipation. This parameter change is implemented through a precharge circuit that sets the bitline voltage to half the supply voltage during the precharge phase, directly addressing the power consumption issue while attempting to maintain operational stability through complementary circuit modifications.
2Use of energy by moving object
If Vdd/2 bitline precharge scheme is applied to conventional 6T SRAM, then power dissipation is reduced, but noise margin deteriorates leading to unstable read operations
Solution Approach 1:
The patent introduces asymmetry by implementing different precharge voltages for the two bitlines (BL and BLB). One bitline is precharged to Vdd/2 while the other maintains different voltage levels, creating an asymmetric configuration that improves noise margin. Additionally, the word line voltage is asymmetrically boosted during write operations to ensure reliable data transfer despite the reduced precharge voltage.
Solution Approach 2:
The patent employs dynamic voltage adjustment where the word line voltage is boosted above Vdd during write operations to ensure reliable data writing. This dynamic adjustment compensates for the reduced bitline precharge voltage, maintaining adequate noise margin and operational stability while benefiting from lower power dissipation during read operations.
3Device complexity
If conventional 6T SRAM is used for massively parallel operations, then simple design is maintained, but power dissipation increases significantly
Solution Approach 1:
The patent modifies the operating voltage parameters of the conventional 6T SRAM by implementing Vdd/2 bitline precharge and boosted word line voltages. These parameter changes reduce the power dissipation per memory cell during parallel operations while maintaining the simple 6T structure, enabling scalable deployment in massively parallel AI chip applications without proportionally increasing total power consumption.
Data Source
AI summary
A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.