Semiconductor Storage Device Bank Write Timing Control
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in efficiently managing data write operations across multiple banks, leading to potential power shortages and incorrect data writing due to simultaneous write operations, especially when receiving a pre-charge all bank command.
Innovation Solution
Incorporating a delay controller that issues write commands for banks at intervals, preventing simultaneous write operations across all banks and controlling the timing of data writes to ensure sufficient power and accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write commands are issued to all banks simultaneously, then data writing speed is improved, but power consumption increases and may cause power shortages
Solution Approach 1:
The patent segments the write operations across multiple banks by introducing a delay controller that staggers the issuance of write commands to different banks. Instead of simultaneously activating all banks, the controller divides them into groups and activates them sequentially with controlled intervals, thereby reducing peak power consumption while maintaining overall writing throughput.
Solution Approach 2:
The patent implements periodic action by using a delay controller to issue write commands to different banks at predetermined intervals. This periodic staggering of write operations ensures that power consumption is distributed over time rather than concentrated in a single peak, preventing power shortages while still achieving efficient data writing across all banks.
2Productivity
If write commands are issued to all banks simultaneously, then data writing throughput is improved, but data writing accuracy deteriorates due to incorrect data writing
Solution Approach 1:
The patent segments the bank activation process to prevent simultaneous write operations that could cause data corruption. By dividing banks into separate groups and activating them sequentially through a delay controller, the system ensures that each bank receives write commands at appropriate intervals, thereby maintaining data writing accuracy while preserving overall throughput.
Solution Approach 2:
The patent applies preliminary action by using the delay controller to prepare and sequence write command issuance before actually writing data to banks. The controller pre-establishes the timing intervals and command sequence, ensuring that each bank is ready to receive write commands at the correct moment, thus preventing incorrect data writing while maintaining efficient throughput.
3Use of energy by moving object
If write commands are issued with intervals, then power consumption is reduced, but data writing time increases
Solution Approach 1:
The patent uses periodic action with optimized intervals in the delay controller to balance power consumption and writing time. By carefully tuning the delay periods between write commands to different banks, the system achieves sufficient power reduction to prevent shortages while minimizing the total time required to complete data writing across all banks.
Solution Approach 2:
The patent applies dynamics by making the delay intervals adjustable and adaptable. The delay controller can dynamically optimize the timing between write commands based on system conditions, power availability, and data size, thereby achieving an optimal balance between reduced power consumption and acceptable data writing time without fixed rigid delays.
Data Source
AI summary
A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.