SRAM Write Data Path Circuit for Yield Enhancement
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Solution Overview
Problem
As semiconductor feature sizes decrease, SRAM memory cells experience increased resistance and performance variations, leading to unreliable write operations due to higher bit line and gate resistances, which hinder the ability to perform write operations effectively.
Innovation Solution
A memory apparatus with a multiplexer and pull-up circuit that selects the non-zero bit line during write operations, clamping it to the power rail voltage to increase the voltage difference between bit lines, thereby enhancing write performance and reducing the need for boost capacitance, which decreases area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are decreased to increase memory density, then more data can be stored in a given area, but resistance of bit lines and gate resistances increase significantly, causing unreliable write operations
Solution Approach 1:
The pull-up circuit activates before the write operation to pre-charge the non-zero bit line to a higher voltage level. This preliminary action ensures that when the write operation commences, the bit line is already at an optimized voltage state, compensating for the increased resistance effects at smaller feature sizes and enabling reliable write operations despite the miniaturization.
Solution Approach 2:
The invention dynamically changes the voltage parameter of the bit line by using the pull-up circuit to clamp the non-zero bit line to a higher voltage level during write operations. This parameter change compensates for the increased resistance at smaller feature sizes, maintaining sufficient voltage differential across the memory cell for reliable write operations while preserving the benefits of reduced feature size for increased density.
2Reliability
If traditional write assist techniques are used to overcome resistance issues, then write operations can be improved, but large boost capacitances are required, increasing area and power consumption
Solution Approach 1:
Instead of using large boost capacitances to temporarily increase voltage, the invention changes the approach by using a pull-up circuit that actively maintains a higher voltage level on the non-zero bit line during write operations. This parameter change in voltage management eliminates the need for large boost capacitances, reducing both area and power consumption while maintaining write operation reliability at smaller feature sizes.
Solution Approach 2:
The invention replaces the mechanical/electrical system of large boost capacitances with an active pull-up circuit implementation. This substitution uses transistors and voltage control mechanisms instead of large capacitive structures, achieving the same write assist function with significantly reduced area and power overhead.
Data Source
AI summary
A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.