Signal Synchronization in Multi-Voltage Memory Domains
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Solution Overview
Problem
Existing integrated circuit designs face challenges in signal synchronization across multiple voltage domains, leading to increased current consumption, timing degradation, and reduced trackability due to desynchronization of signal paths, particularly at lower voltage levels.
Innovation Solution
Implementing a control signal generator with level shifters to synchronize control signals across identical voltage domains, ensuring that read/write and clock signals are driven at periphery supply levels, while wordline signals are driven at core supply levels, thereby maintaining constant delays and reducing peak and average current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate dual power supply is used for SRAM arrays to improve stability and tracking performance, then stability and tracking performance are improved, but device complexity increases
Solution Approach 1:
The patent segments the power supply into separate dual power supplies for SRAM arrays, with different voltage levels for different functional blocks. This segmentation allows independent optimization of stability and tracking performance for each block while managing overall system complexity through modular architecture.
Solution Approach 2:
Different regions of the SRAM array are provided with different power supply voltages tailored to their specific functional requirements. Core SRAM cells receive one voltage level optimized for stability, while peripheral circuits receive another voltage level optimized for tracking performance, achieving local quality optimization.
2Volume of moving object
If supply voltage is reduced below a certain voltage level to enable miniaturization, then miniaturization is achieved, but ability to read and write memory is lost
Solution Approach 1:
The patent employs parameter changes by providing different voltage levels to different parts of the memory system. Core supply voltage is optimized for stability while peripheral supply voltage enables reading and writing operations, allowing the system to operate at reduced voltages for miniaturization while maintaining functional reliability through appropriate voltage selection.
3Reliability
If control signals traverse different voltage domains through different level shifters, then signal paths can be synchronized, but timing degradation and increased current consumption occur
Solution Approach 1:
The patent merges the level shifting functionality into a unified control signal generator that coordinates all control signals. By combining multiple level shifting operations into a single coordinated system, the patent achieves signal synchronization across different voltage domains while minimizing redundant level shifting stages that would cause timing degradation and increased current consumption.
Data Source
AI summary
A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.