Semiconductor Memory Device Asymmetric Bit Line Configuration
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Solution Overview
Problem
In semiconductor memory devices, particularly SRAMs, increasing reading speed while minimizing the enlargement of the layout area is challenging due to the need for balancing the number of bit lines and sense amplifiers, which affects parasitic capacitance and wiring pitch.
Innovation Solution
The solution involves providing a semiconductor memory device with a configuration where the number of bit lines connected to the common read data lines is smaller than those connected to the common write data lines, allowing for shared write and sense amplifiers, thereby reducing parasitic capacitance and minimizing the layout area expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of bit line pairs associated with common read data lines is decreased to increase reading speed, then reading speed is improved, but the number of sense amplifiers and write amplifiers increases, causing enlargement of layout area
Solution Approach 1:
The patent applies asymmetry by differentiating the number of bit line pairs associated with common read data lines versus common write data lines. Specifically, fewer bit line pairs are connected to read data lines compared to write data lines, creating an asymmetric configuration that optimizes reading speed without requiring proportional increases in amplifier count for write operations.
Solution Approach 2:
The patent implements local quality by applying different connection configurations to different functional blocks. The read function uses a reduced number of bit line pairs per common read data line to speed up reading, while the write function maintains a larger number of bit line pairs per common write data line to preserve write capability, allowing each function to be optimized independently.
2Device complexity
If one sense amplifier is disposed for a pair of bit lines in SRAM, then the configuration is simple, but the layout area increases
Solution Approach 1:
The patent merges multiple bit line pairs to a single common read data line pair, allowing one sense amplifier to serve multiple bit line pairs during read operations. This consolidation reduces the total number of sense amplifiers required compared to dedicating one sense amplifier per bit line pair, thereby reducing layout area while maintaining functional capability.
Solution Approach 2:
The common read data line pair and its associated sense amplifier serve multiple bit line pairs, making the sense amplifier multi-functional. This universal approach allows a single sense amplifier to handle reading from multiple different bit line pairs, reducing the overall count of amplifiers needed in the memory mat.
3Object-affected harmful factors
If the number of common read data line pairs is increased to reduce parasitic capacitance, then parasitic capacitance is reduced, but the number of sense amplifiers and write amplifiers must increase, enlarging layout area
Solution Approach 1:
The patent creates an asymmetric configuration where the number of bit line pairs per common read data line is intentionally reduced below the conventional equal distribution. This asymmetric arrangement reduces the total capacitance load on read data lines, improving reading speed without requiring additional sense amplifiers to compensate, thus avoiding layout area enlargement.
Data Source
AI summary
The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.