Common Leveling for 4-Bit Wide DRAM Strobe Signals
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Solution Overview
Problem
In memory controllers interfacing with multiple DRAM devices, achieving common read and write leveling for 4-bit wide DRAMs is complex due to different data widths and arrival times of clock, command, control, and address signals, requiring multiple leveling settings and additional logic, area, and power.
Innovation Solution
A mechanism is introduced to align two strobe signals (DQS0 and DQS1) serving one byte, allowing for common read and write leveling settings by deskewing the strobe signals before deskewing the data bits, using read and write deskew training processes that adjust delay lines to align DQS1 with DQS0, enabling a single set of leveling settings for the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate leveling settings are used for each DQS signal in ×4 mode, then data alignment precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the leveling settings for DQS0 and DQS1 by using a common reference clock and applying the same delay adjustment to both strobe signals. This is achieved by controlling both DQS signals from a single clock source and using unified delay logic, thereby reducing the number of independent leveling settings from two to one while maintaining adequate data alignment precision.
Solution Approach 2:
The patent implements a universal leveling mechanism that can handle both ×4 and ×8 modes using the same control logic and delay structures. The common leveling setting serves multiple functions: it aligns both DQS0 and DQS1 in ×4 mode, and provides the basis for DQ alignment in both operating modes, eliminating the need for mode-specific leveling circuits.
2Measurement precision
If separate leveling settings are used for each DQS signal in ×4 mode, then data alignment precision is improved, but power consumption increases
Solution Approach 1:
The patent combines the power-consuming leveling adjustment operations into a single unified process. Instead of independently adjusting and validating leveling settings for DQS0 and DQS1, the system performs one common leveling adjustment that simultaneously optimizes both signals, thereby reducing the total number of adjustment operations and associated power consumption.
Solution Approach 2:
The patent discards the redundant separate leveling control logic for DQS1 in ×4 mode, recovering the power that would have been consumed by maintaining and adjusting independent leveling settings. The single common leveling setting is reused for both DQS signals, eliminating wasted power in duplicate control circuitry and adjustment operations.
3Adaptability or versatility
If fly-by topology is used for clock distribution, then signal distribution capability is improved, but signal arrival time skew increases
Solution Approach 1:
The patent applies preliminary delay adjustment to the clock signals before they are distributed to the DQS generation logic. By pre-adjusting the clock phases and delays in a controlled manner, the system compensates for the inherent skew introduced by the fly-by topology, ensuring that both DQS0 and DQS1 arrive at their respective latches at the correct time despite the physical distribution delays.
Solution Approach 2:
The patent dynamically adjusts the clock frequency, phase, and delay parameters to optimize signal arrival timing. By changing these parameters based on the fly-by topology characteristics, the system compensates for signal skew and maintains precise timing alignment across all memory devices in the channel, thereby resolving the timing precision issue while preserving the scalability benefits of fly-by topology.
Data Source
AI summary
Systems and methods of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.