1P2N Pre-Decoder Circuitry for Low-Power Memory Cell Selection
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Solution Overview
Problem
Existing memory devices utilizing 1P1N bi-polar decoders for resistance variable memory cells exhibit high power consumption due to significant changes in gate biases during polarity transitions, which is inefficient and wasteful.
Innovation Solution
Implementing decoder circuitry with one p-type transistor and two n-type transistors (1P2N bi-polar decoders) to provide selection and de-selection signals, which reduces power consumption by maintaining stable gate biases during polarity transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If 1P1N bi-polar decoders are used for resistance variable memory cells, then the memory device can perform basic selection and de-selection operations, but power consumption increases due to significant changes in gate biases during polarity transitions
Solution Approach 1:
The decoder is segmented into multiple transistor components (one p-type transistor and two n-type transistors) that can be independently controlled. This segmentation allows separate control of selection and de-selection functions, enabling stable gate bias maintenance during polarity transitions and reducing power consumption compared to the conventional 1P1N design.
2Loss of energy
If gate biases are changed significantly during polarity transitions in 1P1N decoders, then selection and de-selection signals can be provided, but energy efficiency decreases
Solution Approach 1:
The invention changes the bias parameters of the transistor gates to maintain stability during polarity transitions. By adjusting the gate bias voltages of the p-type and n-type transistors appropriately, the decoder can switch between positive and negative configurations without significant bias changes, thereby improving energy efficiency while maintaining operational simplicity.
Data Source
AI summary
The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.