Logic Circuits Characterised By Logic Function TRIZ Cases

An asymmetrical SR latch POR circuit cuts power use while keeping reset active during slow supply voltage ramp-up.

A timing control circuit uses a first clock to count refresh events and trigger ECS commands accurately for complete DRAM scrub operations.

Concurrent composite assignments let processors update shared memory cells without locks, preserving deterministic results and reducing contention.

Asymmetric detection cells placed within laser spot range of protected logic trigger rapid shutdown against laser fault injection.

Sequenced clock gating with OR-based switching prevents glitches, cuts component count, and preserves clock quality at higher data rates.

Alternating gate bias states in a differential pair cancel DC stress, limiting MOSFET NBTI/PBTI drift without enlarging the circuit.

Three folded ramps at different common mode levels extend signal capture beyond two-ramp limits, cutting noise sensitivity and harmonic distortion.

A two-stage MRAM encoder uses a 7:1 decoder and logic input swapping to shrink unary-code area and cut standby current.

A dual-fuse eFuse with shared NMOS paths improves read correctness while lowering programming voltage, current, power, and area.

Series CML stages and feedback data latches boost DDR5 signal amplification, cut propagation delay, and align data with divided strobe timing.

A tracking circuit pre-switches stacked transistors in an output buffer to prevent drain-source overvoltage and improve reliability.

Asynchronous sanitizing circuits clean glitchy non-persistent requests before MUTEX arbitration, enabling scalable low-latency handling.

Count-based supplementary refresh protects DDR5 SDRAM from row hammer risk during frequent all-bank and same-bank refresh mode switching.

Closed-loop gain control in a reference-voltage equalization input buffer cuts DRAM I/O power while preserving high-speed signal equalization.

A ring oscillator turns hard-to-measure DTC timing behavior into frequency data, enabling precise PLL self-test with low interference.

A control and switch module reconfigures motherboard pin connections so different graphics card pin functions can work reliably on one board.

Simultaneous phased-clock selection boosts serial slew rate and helps transmitter circuits overcome clock-skew limits during parallel-to-serial conversion.

Complementary ring oscillators and output feedback calibration reduce discontinuous pulses and jitter at high frequency multiples.

A capacitor-comparator clock detector checks image sensor input frequency with less hardware, lower power, and more stable output.

A shift register compares current and prior reference-clock states to detect radiation-induced glitches and trigger backup clock switching.

Capacitors and resistors form a low-pass path that limits ring oscillator input voltage swings, protecting MOS transistors during startup.

Memristor-set CMOS switch points enable low-power, small-area fuzzy template matching for real-time in-vivo neural spike sorting.

Connecting the virtual nodes of two clock drivers preserves fast clock edges and avoids internal circuit malfunctions at higher frequencies.

A tunable RC control path isolates glitch filtering from the data path to suppress sub-50 ns noise spikes without duty cycle distortion.

A receiver pull-down circuit grounds ringing-induced peaks from parasitic capacitance to prevent false data detection in transformer links.

A calculation and correction circuit detects P/N voltage differences and corrects asymmetric crosstalk to prevent error characters in serial links.

Two-stage chip select sampling separates 2T CMD and NT ODT pulse widths to prevent DRAM command decoding errors.

Customized MSB skipping and LSB truncation cut ADC power in analog MAC channels while preserving matrix multiplication accuracy for edge AI.

Inverted VDD/VSS delay elements and switched metal lines achieve target delay with fewer transistors, less area, and shorter routing.

Shared control signals and flip-flop scan chains simplify routing to non-volatile bits while enabling synchronized read and write operations.

Non-overlapping clock generation and direct main clock input cut timing skew in interleaved ADC sampling while improving speed and hardware efficiency.

Integrated weight buffers inside each CIM memory bank allow weight updates and computation to run together, cutting time, power, and chip area.

Staged clock delays open the transmission gate before the gated input switches, improving flip-flop timing reliability under edge variation.

Separate NMOS and PMOS supply sequencing stabilizes EEPROM decoder latches at low voltage while avoiding prohibited states and gate oxide stress.

Parallel delay and inversion branches eliminate glitches during delay code changes, enabling continuous high-speed signal transmission.

Dual carrier channels across capacitive barriers balance delay and current draw while filtering common mode transients and removing jitter.

Light pulses encoded by carrier-envelope phase drive probe-structure currents, pushing logic operations beyond electronic speed limits.

A low-bandwidth test mode simulates reduced transmitter drive strength to expose glitches and missed bits in digital isolators.

Sanitizer and MUTEX circuits stabilize glitchy non-persistent requests, enabling lower-latency and more reliable signal arbitration.

Two-stage EQ boosts duobinary transitions and then saturates signal levels to cut power use and frequency loss in high-speed communication.

Pulse-driven forward and backward latching modes enable concurrent in-memory arithmetic while isolating units to improve IC speed and reliability.

Specific word-line voltage control enables XNOR in standard NAND flash, avoiding extra bit lines and separate sense amplifiers.

Positive and delayed feedback generate narrow spike pulses while minimizing current flow to cut power use in neuron-style circuits.

Stair-step edge shaping with selectable delay chains reduces overshoot, undershoot, and eye closure on long 3DIC data paths.

Controlled approximate additions in a dot-product accumulator generate LWE errors without TRNG or PRNG hardware, cutting circuit size and energy.

Memristor-based self-organizing logic gates use reverse logic and dynamic correction to solve NP problems with polynomial resources.

Stable gate-bias control in a 1P2N pre-decoder cuts polarity-transition power loss while preserving memory cell selection and de-selection.

A series decap and filtered bias circuit stabilizes rail voltage swings to limit thin-oxide MOSFET breakdown and leakage in high-frequency chips.

A cross-coupled latch and decision circuit generates reset pulses from actual state transitions, enabling stable low-voltage initialization.

Using AC voltages with three logic states, this case shows how trinary logic can raise computing power while avoiding binary scaling limits and leakage.

Integrated phase detection and calibration correct differential signal skew in DRAM, easing PCB wiring constraints while improving signal quality.

Pulse and sustain input stages help a level shifter resist parasitic-capacitance errors from high-voltage ground changes and keep output stable.

Digital counters switch resistive circuits in RPU crosspoints to store ANN weights with more symmetric updates, lower power use, and faster training.

Byte-level and cross-byte check codes improve DRAM error correction while lowering ECC hardware complexity, power use, and encoding delay.

Pulse-controlled compensation adds current during signal transitions to raise DRAM output slew rate and support higher memory transmission speed.

Multiple phase clocks and warming-up cycle masking refine memory data output timing, preserving margin for stable high-speed operation.

A static CMOS full adder cuts 3-transistor stacks to 2, separates carry logic, and lowers input capacitance, delay, and area.

Same-sign floating-point adders handle matching-sign operands first, cutting power and silicon area while preserving mixed-sign addition speed.

Automatic clock generation on interrupt assertion prevents missed safety fault signals while cutting microcontroller power in low-power modes.

A power management circuit shuts down the bitcell array during DVS scans while keeping memory periphery active to expose faults without temperature spikes.

Multi-cycle partial product generation and early accumulation cut CIM Booth multiplication latency while reducing hardware complexity.

Partially toggled data selection signals cut transistor switching in a transmitter serializer, lowering power while preserving serial output timing.

Threshold-based data inversion cuts bit switching on storage data lines, lowering power use while preserving write accuracy.

A clock detector disables duty-cycle correction when the input clock stops, preventing error saturation and restoring accurate timing on reactivation.

Column-wise in-situ DRAM matching cuts k-mer data movement and latency with parallel comparison and early row termination.

Compensating buffer duty skew from external voltage levels helps receiver circuits keep stable output characteristics across low- and high-speed modes.

Cross-coupled OAI and AOI gates replace the scan multiplexer to cut inversions, transistor count, power use, and delay in flip-flops.

A delayed inverter and switch generate narrow spike pulses with steep edges while cutting power use in neural spike circuits.

Digital deglitching removes comparator glitches from supply spikes in class-D amplifiers without extra high-frequency clocks or filters.

A lock circuit and level shifter switch between brief fuse-programming voltage and a safe intermediate level to protect 5 nm devices.

A current-mirror single-stage circuit shifts sub-threshold digital inputs across a wide voltage range with lower area, power, and delay.

Pulse detectors compare signal widths to a timing aperture to catch microelectronic glitches early and prevent unreliable operations.

Calculates carry indicator bits directly on masked binary data using XOR and add/subtract logic, avoiding unmasking delays and reliability loss.

By disabling some I/O ports and sequentially multiplexing test data, the circuit cuts tester port demand while preserving memory test coverage.

A shared common module drives XOR and XNOR outputs in less area, speeding DRAM error detection and correction.

Parallel transfer logic stages speed fixed-value addition while keeping circuit area and power low for normalization and rounding.

Merged 2's complement and rounding logic shortens the FMA mantissa path while preserving floating-point accuracy.

Digital sampling replaces analog phase detection to avoid layout-mismatch errors, reduce latency jumps, and keep the delay lock loop locked.

A balloon latch on an independent power rail preserves register data when the main flip-flop supply is shut off, cutting power use.

Per-lane duty correction and variable delay align clock gating timing to suppress jitter, prevent glitches, and keep multi-lane clocks synchronized.

A logic-gated bit cell and perpendicular second word line enable selective programming without activating full rows or columns, cutting array power.

Divider and gating stages create reduced-duty quadrature clock signals with low phase noise and IQ matching while cutting LO power use.

An oriented RWL-integrated CIM bit cell layout initializes product nodes to improve MAC uniformity, reliability, and array area efficiency.

State-dependent pulldown timing lets a bi-directional bus repeater avoid self-locking during simultaneous high-to-low transitions.

Delayed differential amplitude coding and a variable-capacitor LC network relax RF timing limits while extending tuning range and efficiency.

Quadrature edge detection helps a CDR circuit lock clock frequency and phase to varying data rates while avoiding repeated resets and excess power.

A buffer circuit compares target and readout data during writing, removing separate comparison hardware and reducing memory circuit area.

Selective deactivation of arithmetic modules cuts ANN compute energy and heat in mobile devices while keeping precision adjustable.

Equalized edge-combiner loading helps a DLL avoid false locks while improving output clock precision and lock stability.

A tristate driver replaces buffer stages in a master-slave flip-flop to cut clock delay, preserve drive strength, and reduce setup time.

Test cells enable differential boot reads, while averaged reference-cell currents support accurate single-ended NVM reads and data security.

Level shifters and dual-rail power control let memory circuits switch across voltage domains with lower power use and automatic sleep states.

Continuous current drives conserved skyrmions through nanowire logic gates, avoiding repeated creation and cutting energy dissipation.

A ring-oscillator coarse/fine detector helps DPLLs lock faster with lower jitter while cutting delay-chain size, power, and die space.

Mode-switching MOSFETs activate CMOS parasitic capacitance to stabilize power supply voltages without added decoupling capacitors.

Multiphase δ-sequence SBS generation spreads ones evenly to improve multiplication accuracy while reducing string length and hardware overhead.

Reused intermediate signals let sum and carry-out compute with fewer primary-input transistors, cutting capacitance, power, area, and delay.

A reversible current mirror helps a low-voltage level shifter cut transition delay, power use, and area in subthreshold logic.

Redundant registers detect inconsistent states and trigger reset only when needed, preserving stable startup under voltage fluctuations.

A three-state chopper clock path uses only rising edges to cut duty cycle distortion, current draw, and input capacitance.