Spike Generation Circuit With Feedback-Delayed Narrow Pulse Output
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Solution Overview
Problem
Spike generator circuits, such as neuron circuits, face challenges in reducing power consumption.
Innovation Solution
The proposed spike generation circuit includes a CMOS inverter connected between power supplies, a switch, an inverting circuit, and a delay circuit, with configurations that apply positive and negative feedback to generate narrow pulse-width spike signals, reducing power consumption by minimizing current flow through feedback loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional spike generator circuits are used, then spike signal generation is achieved, but power consumption is high
Solution Approach 1:
The patent applies positive feedback through the first inverting circuit that feeds back to the control terminal of the switch, and negative feedback through the delay circuit that feeds back to the input node of the CMOS inverter. This feedback mechanism enables the circuit to generate narrow pulse-width spike signals by rapidly switching between states, thereby minimizing current flow through the feedback loops and reducing overall power consumption while maintaining reliable spike signal generation
Solution Approach 2:
The circuit generates spike signals through periodic switching action controlled by the feedback mechanisms. The switch alternates between on and off states in response to the inverted and delayed feedback signals, creating periodic spike outputs. This periodic switching minimizes the duration of current flow, reducing power consumption while maintaining the necessary spike generation capability
2Use of energy by moving object
If feedback loops are present in the circuit, then spike signal generation is enabled, but current flow increases power consumption
Solution Approach 1:
The patent introduces intermediary elements including the first inverting circuit that inverts the feedback signal before returning it to the control terminal, and the delay circuit that delays the feedback signal before returning it to the input node. These intermediaries enable the feedback loops to function with minimal current flow by controlling the timing and polarity of feedback signals, thus reducing power consumption while managing circuit complexity through functional decomposition
Data Source
AI summary
A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.