Scan Chain Interface for Non-Volatile Bits With Shared Control Routing
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Solution Overview
Problem
The challenge of routing individual control signals to each non-volatile distributed storage bit becomes increasingly difficult as the number of bits to be implemented in a chip increases, particularly in applications like field-programmable gate arrays and neural networks, due to the need for independent signal propagation for operations such as read, write, and one-time programming.
Innovation Solution
A scan chain serial interface is introduced, allowing multiple non-volatile storage bits to share control signals through logic circuitries like flip-flops and latches, synchronized by a clock signal, enabling simultaneous execution of operations like read and write across groups of bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If individual control signals are routed to each non-volatile distributed storage bit, then each bit can be independently controlled for operations, but the routing complexity increases significantly as the number of bits increases
Solution Approach 1:
Multiple non-volatile storage bits are grouped into banks, and control signals are merged to operate on multiple bits simultaneously. Instead of routing separate control signals to each bit, a single control signal is shared across a bank of bits, reducing the number of control signal routes while maintaining independent operational capability through the bank structure
Solution Approach 2:
Control signals are designed with multi-functionality to serve multiple storage bits within a bank. The same control signal performs the same operation across multiple bits, allowing universal control rather than dedicated control for each bit, thereby simplifying routing while preserving operational versatility
2Quantity of substance
If the number of non-volatile distributed storage bits is increased, then storage capacity is improved, but the difficulty of routing control signals to each bit increases
Solution Approach 1:
The large number of storage bits is segmented into multiple banks, each bank managed by its own control signal. This segmentation allows the system to scale storage capacity by adding more banks without proportionally increasing routing complexity, as each bank uses a standardized control signal approach
Solution Approach 2:
Control signals are merged to operate on multiple bits within each bank simultaneously. This combining approach allows the system to increase storage capacity by expanding the number of bits per bank or number of banks, while the control signal routing scales more efficiently than a one-to-one mapping would require
Data Source
AI summary
A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.