In-Situ DRAM k-Mer Matching With Column-Wise Parallel Comparison
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current k-mer matching algorithms in bioinformatics are memory-bound and cache-unfriendly, leading to performance bottlenecks in genome analysis due to high data access latency and energy consumption, especially with the rapid growth of genomic databases, making existing compute-centric platforms like CPUs and GPUs inadequate for large-scale genome analysis tasks.
Innovation Solution
The design of Sieve, a high-performance in-situ DRAM-based accelerator that uses column-wise data mapping and early termination mechanisms to accelerate k-mer matching, integrating custom logic into DRAM to reduce latency and energy overhead by comparing query k-mers with thousands of reference k-mers simultaneously and terminating row activation upon mismatch detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If compute-centric platforms (CPU/GPU) are used for k-mer matching, then computational flexibility is maintained, but data access latency and energy consumption increase significantly
Solution Approach 1:
The patent merges the memory storage function with the computation function by integrating k-mer matching logic directly into the DRAM device. This allows data to be stored and processed in the same location, eliminating the need for data transfer between memory and compute units, thereby reducing both energy consumption and access latency.
Solution Approach 2:
The patent introduces an intermediary processing layer between the CPU/GPU and the DRAM memory. This intermediary handles the k-mer matching operations locally within the memory device, acting as a mediator that reduces the computational burden on the CPU/GPU while minimizing data access requirements.
2Productivity
If conventional row-wise data mapping is used in DRAM, then simplicity of implementation is maintained, but matching efficiency decreases due to inability to perform simultaneous comparisons
Solution Approach 1:
The patent inverts the conventional row-wise data mapping approach by using column-wise mapping instead. This inversion allows multiple reference k-mers to be stored in the same row across different columns, enabling simultaneous comparison of query k-mers against thousands of reference k-mers in parallel when the row is activated.
Solution Approach 2:
The patent changes the data organization from a two-dimensional row-wise structure to a column-wise structure that exploits the vertical dimension of DRAM bitlines. This dimensional change enables parallel comparison operations by allowing multiple reference sequences to be accessed simultaneously through the same row activation but different column selections.
3Reliability
If all rows are activated for complete matching, then matching accuracy is ensured, but energy consumption and time increase due to unnecessary processing of mismatched rows
Solution Approach 1:
The patent applies partial action by activating only the necessary portion of rows required for matching. Instead of activating all rows in the DRAM device, the system activates only those rows containing reference k-mers that need to be compared with the query, thereby reducing energy consumption while maintaining matching accuracy for the relevant data.
Solution Approach 2:
The patent segments the DRAM device into multiple banks, where each bank contains a subset of reference k-mers. This segmentation allows the system to activate only the specific banks that contain relevant reference sequences for the current query, rather than activating the entire memory device, thus reducing both energy consumption and access time while preserving matching accuracy.
Data Source
AI summary
Apparatus includes a plurality of memory cells (e.g., a dynamic random access memory (DRAM)) addressable as rows and columns and a plurality of matching circuits configured to be coupled to respective bit lines associated with the columns A control circuit is configured to store respective reference sequences (e.g., binary-encoded k-mer patterns) in respective ones of the columns, to sequentially provide rows of bits stored in the memory cells and bits of a query to the matching circuits, and to identify one of the reference sequences as corresponding to the query responsive to comparisons by the matching circuits.