DDR PHY Clock Gating Architecture for Glitch-Free Clock Switching
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Solution Overview
Problem
Clock switching and gating in systems can generate glitches that cause timing issues, and using glitch-free multiplexers increases component count, degrading clock quality.
Innovation Solution
A system utilizing OR gates and clock gating circuits to sequence clock gating functions, preventing glitches while reducing component count, thereby improving clock quality and meeting tighter timing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If glitch-free multiplexers are used to prevent timing issues during clock switching, then timing reliability is improved, but device complexity increases due to increased component count
Solution Approach 1:
The clock switching function is segmented into multiple independent clock gating circuits, each handling a specific clock source. Each gating circuit independently controls its clock source without requiring complex interaction with other gating circuits, thereby eliminating the need for glitch-free multiplexers while maintaining timing reliability during switching operations.
Solution Approach 2:
Clock gating circuits serve as intermediary elements between clock sources and the rest of the system. These gating circuits mediate the clock switching process by using control signals to selectively pass or block clock signals, replacing the need for complex glitch-free multiplexer circuits while ensuring clean transitions without glitches.
2Device complexity
If more clock gating circuits are added to reduce component count, then device complexity decreases, but the risk of timing issues and glitches may increase
Solution Approach 1:
The system divides clock management into separate, independent gating circuits for each clock source. This segmentation allows each circuit to be simple and minimal in components, while the collective system achieves reliable glitch-free switching through the coordinated operation of these simple circuits under central control.
Solution Approach 2:
The system uses control signals that provide feedback mechanisms to manage the state of multiple clock gating circuits. These control signals ensure that gating circuits transition in a coordinated manner, preventing timing issues and glitches while maintaining simple circuit designs with minimal component count.
Data Source
AI summary
In certain aspects, a system includes a first clock source configured to generate a first clock signal, a second clock source configured to generate a second clock signal, a clock path, and an OR gate having a first input, a second input, and an output, wherein the output of the OR gate is coupled to the clock path. The system also includes a first clock gating circuit coupled between the first clock source and the first input of the OR gate, and a second clock gating circuit coupled between the second clock source and the second input of the OR gate.