Delay Circuit Layout Using Inverted Power Paths to Cut Area
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Solution Overview
Problem
Existing delay circuits require significant resources and area due to the use of many transistors and long metal lines to achieve desired delay times, which is inefficient with the increasing integration and shrinking scale of electronic devices.
Innovation Solution
A delay circuit design utilizing power switches and delay elements configured with alternating NAND and NOR gates, where power sources are inverted to optimize delay times and reduce resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If traditional delay circuits use many transistors and long metal lines to achieve desired delay time, then the delay time can be extended, but the resource consumption and area usage increase significantly
Solution Approach 1:
The patent changes the operating parameters of the delay circuit by inverting the power sources (swapping VDD and VSS connections) to different delay elements. This parameter change enables different delay elements to operate with inverted power supply polarities, creating asymmetric delay paths that can achieve the desired delay time with fewer transistors and shorter metal lines, thus reducing resource consumption while maintaining the required delay duration
2Duration of action of moving object
If traditional delay circuits use many transistors and long metal lines to achieve desired delay time, then the delay time can be extended, but the area occupied increases
Solution Approach 1:
The patent merges multiple delay elements into a compact integrated circuit structure where delay elements are arranged in parallel configurations with shared power supply networks. By inverting power sources to different delay elements, the design creates a space-efficient layout that achieves the required delay time without requiring proportionally longer metal lines or additional transistor count, thereby reducing the overall area occupied by the delay circuit
3Productivity
If power sources are inverted in delay elements, then transition times are reduced and resource efficiency improves, but the circuit complexity increases
Solution Approach 1:
The patent applies inversion by swapping the VDD and VSS power supply connections to different delay elements within the same integrated circuit. This inversion strategy creates asymmetric delay paths where some delay elements operate with inverted power polarities, enabling faster transition times and improved resource efficiency. The complexity increase is managed through systematic arrangement of inverted and non-inverted delay elements, maintaining design regularity while achieving performance improvements
Data Source
AI summary
A circuit is provided. The circuit comprises a first power switch, a second power switch and delay elements. The first power switch adjusts a first voltage on a first metal line according to an input signal. The second power switch adjusts a second voltage on a second metal line according to the first voltage. The delay elements are coupled between the first metal line and the second metal line, and delay, in response to the adjusted first voltage and the adjusted second voltage, the input signal to generate an output signal.