Static CMOS Full Adder Layout for Lower Delay and Input Loading
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Solution Overview
Problem
Conventional CMOS-based mirror full adders suffer from significant delay and power consumption due to 3-transistor stacking in the sum generation path and heavy loading of input pins, which degrades performance and increases area and power usage in digital integrated circuits.
Innovation Solution
The proposed solution involves a static CMOS-based Full Adder circuit with a carry generation circuit and a carry propagation circuit, optimized to reduce the number of NMOS/PMOS stacks to 2-transistor stacks, separate carry generation logic from carry propagation logic, and limit input pin connections to reduce capacitance and delay, enhancing performance and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If 3-transistor stacking is used in the sum generation path, then the full adder can be implemented with conventional CMOS structure, but the delay significantly increases and performance degrades
Solution Approach 1:
The sum generation path is segmented into multiple stages, with the critical path broken down by introducing intermediate nodes and parallel transistor paths. The 3-transistor stack is divided into 2-transistor stacks arranged in parallel, allowing signals to propagate through multiple concurrent paths rather than a single long path, thereby reducing the overall delay while maintaining manufacturability.
Solution Approach 2:
The circuit topology transitions from a single-dimensional 3-transistor stack to a two-dimensional arrangement of parallel 2-transistor stacks. This dimensional change allows signals to propagate through multiple spatial paths simultaneously, reducing the effective signal path length and delay while preserving the conventional CMOS manufacturing process.
2Ease of operation
If input pins are connected to multiple MOS transistors (8 for AB, 6 for CI), then the full adder logic can be fully implemented, but the input capacitance increases and preceding stage is heavily loaded
Solution Approach 1:
The input pin connections are segmented into multiple groups, each driving a subset of transistors. Instead of all 8 transistors for AB inputs being directly connected to the same input pins, the transistors are arranged in parallel groups where each group is driven by dedicated input connections, distributing the capacitive load across multiple smaller groups and reducing the total input capacitance.
Solution Approach 2:
Intermediate nodes and buffer transistors are introduced between the input pins and the logic transistors. These intermediaries act as mediators that drive smaller capacitive loads, allowing the full adder logic to be implemented without directly loading the preceding stage with the full capacitance of all 8 transistors.
3Area of stationary object
If carry propagation circuit and carry generation circuit are combined in a single stage, then the circuit area is reduced, but the delay in carry output arcs significantly increases
Solution Approach 1:
The carry output generation is segmented into distinct carry propagation and carry generation stages that operate in parallel rather than being combined in a single sequential stage. This segmentation allows the carry signal to be generated and propagated simultaneously through different circuit paths, reducing the overall delay while the compact arrangement of these parallel stages maintains efficient area utilization.
Solution Approach 2:
The circuit architecture transitions from a single-stage combined carry circuit to a multi-stage parallel architecture where carry propagation and generation occur in separate but concurrent stages. This dimensional reorganization in the time domain allows faster carry output without proportionally increasing area, as the parallel stages can be efficiently laid out.
4Ease of manufacture
If 3 MOS stacking is used in sum generation path, then the conventional CMOS full adder can be implemented, but the area consumption increases
Solution Approach 1:
The sum generation circuit is segmented into parallel 2-transistor stack paths instead of a single 3-transistor stack. This segmentation reduces the height of the transistor stack (from 3 to 2 transistors), allowing for more compact vertical arrangement and reducing the overall area consumption while maintaining compatibility with conventional CMOS manufacturing processes.
Data Source
AI summary
Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder circuit. The integrated circuit includes a carry generation circuit configured to receive a first input and a second input to generate a carry, and a carry propagation circuit configured to receive the first input, the second input, and a third input to generate a propagated output. The integrated circuit further includes a carry output generation circuit configured to receive the generated carry and the propagated output to generate a final carry as an output, and a sum generation circuit configured to generate a sum output. The sum generation circuit includes the carry generation circuit and is configured to receive the first input, the second input, and generated carry to generate an exclusive NOR output, and further uses the generated exclusive NOR output and the third input to generate the sum output.