NAND Flash XNOR Control Using One Sense Amplifier Per Bit Line
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Solution Overview
Problem
Existing NAND flash memory circuits for XNOR operations are incompatible with normal NAND flash memory structures, leading to increased area costs due to the need for separate bit lines and sense amplifiers.
Innovation Solution
A method for controlling NAND flash memory to implement XNOR operations by utilizing a structure compatible with normal NAND flash memory, where synaptic strings are connected to sense amplifiers in a one-to-one correspondence, and specific potential voltages are applied to word lines and drain selectors to read data from associated synaptic strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a sense amplifier is connected to two bit lines for XNOR operation, then the XNOR operation can be implemented, but the structure becomes incompatible with normal NAND flash memory and area cost increases
Solution Approach 1:
The sense amplifier is designed to handle multiple functions: it can perform normal read operations on single bit lines and XNOR operations on paired bit lines. The control logic enables the sense amplifier to switch between these modes based on the operation type, making it a universal component that serves both normal memory access and specialized XNOR computation without requiring separate dedicated hardware for each function.
Solution Approach 2:
The patent merges the XNOR operation functionality into the existing sense amplifier structure by connecting two bit lines to a single sense amplifier. This combination allows the sense amplifier to simultaneously process signals from both bit lines and perform the XNOR operation, eliminating the need for separate XNOR circuitry and reducing overall device complexity.
2Adaptability or versatility
If each bit line is controlled by an individual switch for XNOR operation, then the XNOR operation can be implemented, but the structure becomes incompatible with normal NAND flash memory and area cost increases
Solution Approach 1:
The row decoder is enhanced to serve dual purposes: it performs standard row selection for normal memory operations and simultaneously controls the row selection switches for XNOR operations. By integrating the XNOR control functionality into the existing row decoder, the patent avoids adding separate control circuits, thereby maintaining compatibility with normal NAND flash memory structures while enabling XNOR operations.
Solution Approach 2:
The control functions for normal memory access and XNOR operations are merged into a unified control architecture. The row decoder and its associated row selection switches are used for both standard read operations and XNOR computations, eliminating the need for duplicate control circuitry and reducing the overall area required for control logic.
Data Source
AI summary
The present invention provides a method for controlling a NAND flash memory to implement an XNOR operation. First word lines and second word lines are connected to sense amplifiers in a one-to-one correspondence manner. The XNOR operation of the NAND flash memory is implemented by controlling a data storage mode and a voltage of the word lines.