Chopper Clock Generator Using Rising Edges to Minimize DCD
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Solution Overview
Problem
Generating ultra-low duty cycle distortion (DCD) clock signals is challenging due to mismatches in component characteristics, which affects the correction of DCD jitter in high-speed communication systems, limiting data transmission rates and lengths.
Innovation Solution
A clock signal generator comprising a CMOS clock source, driver, frequency divider, non-overlapping generator circuit, and differential chopper circuit, which generates and processes clock signals to minimize DCD by using only rising edges and reducing resistance and capacitance mismatches through a three-state chopper circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional clock signal generation methods are used, then device simplicity is maintained, but duty cycle distortion (DCD) increases due to component mismatches
Solution Approach 1:
The clock signal generation is segmented into multiple independent paths: a first path generates a first clock signal with specific rise/fall characteristics, while a second path generates a second clock signal with complementary characteristics. By dividing the generation process into separate segments rather than using a single conventional generator, the patent achieves low DCD through the combination of these segmented paths without requiring complex compensation circuits in each individual path.
Solution Approach 2:
The patent deliberately introduces asymmetry by using different circuit configurations for the first and second clock signal generation paths. The first path may use one type of buffer or delay circuit while the second path uses a different configuration, creating asymmetric rise and fall times that when combined produce symmetric output edges. This asymmetric design in separate paths resolves the DCD problem without requiring symmetric matching of components within a single path.
2Manufacturing precision
If component mismatches are reduced to achieve ultra-low DCD, then duty cycle distortion decreases, but manufacturing difficulty and cost increase
Solution Approach 1:
The patent extracts the DCD correction function from the main clock generation path by using a separate correction mechanism. Instead of requiring ultra-precise component matching in the primary clock generators, the invention takes out the distortion correction into a dedicated circuit that processes the already-generated clock signals. This separation allows standard components to be used while achieving ultra-low DCD through the extraction and separate handling of the correction function.
Solution Approach 2:
The patent changes parameters such as delay times, buffer characteristics, and circuit configurations in the correction paths to compensate for component mismatches. By adjusting these parameters in the secondary correction circuits rather than requiring precise parameter matching in the primary generation circuits, the invention achieves low DCD with standard, easily manufactured components. Parameter changes in correction paths are much easier to implement than parameter control in primary generation paths.
3Manufacturing precision
If complex correction circuits are used to reduce DCD jitter, then duty cycle distortion decreases, but current consumption and input capacitance increase
Solution Approach 1:
The patent employs dynamic switching mechanisms that selectively activate correction paths based on the specific distortion characteristics detected in real-time. Rather than continuously operating complex correction circuits that would consume high current, the invention uses dynamic control to engage only the necessary correction elements when needed. This dynamic approach maintains ultra-low DCD performance while minimizing current consumption by keeping correction circuits in a low-power state during normal operation.
Solution Approach 2:
The correction circuits operate periodically rather than continuously, using periodic sampling and correction cycles. The system periodically measures the actual clock signal characteristics and applies corrections only during these scheduled intervals, rather than continuously driving complex correction circuits. This periodic operation mode achieves the required DCD reduction while significantly reducing average current consumption compared to continuous correction circuit operation.
Data Source
AI summary
Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.