SR Latch Power-On Reset Circuit for Slow Supply Ramp-Up
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Solution Overview
Problem
Existing power-on reset systems face issues of high power consumption and failure to enter the reset state when the supply voltage ramps up slowly, leading to ineffective reset operations in SR latch circuits.
Innovation Solution
A low power consumption power-on reset system is designed with an SR latch circuit and an operating circuit that generates a power-on reset signal based on the supply voltage and an enable signal, ensuring the reset state is maintained during slow supply voltage ramp-ups through asymmetrical transistor configurations and pulling circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power-on reset circuit uses a resistor and capacitor configuration, then the circuit can generate a power-on reset signal, but the signal level becomes too low to enter the reset state when the supply voltage ramps up slowly
Solution Approach 1:
The patent employs an asymmetrical transistor configuration where the first transistor has a wider channel width than the second transistor. This asymmetry creates different conduction characteristics that ensure the power-on reset signal can reach the required threshold level even when the supply voltage ramps up slowly, thereby resolving the contradiction between reliable reset state entry and slow voltage ramp rates
Solution Approach 2:
The patent changes the conduction parameters of the transistors by adjusting the channel width ratio between the first and second transistors. This parameter modification optimizes the signal levels at critical nodes, ensuring that the power-on reset signal maintains sufficient amplitude to trigger the reset state regardless of the supply voltage ramp rate
2Reliability
If the power-on reset circuit uses a reference signal generation circuit and comparator, then the reset signal can be generated, but the power consumption becomes excessive
Solution Approach 1:
The patent extracts and eliminates the power-consuming reference signal generation circuit and comparator components from the power-on reset system. By removing these unnecessary components, the design achieves low power consumption while maintaining reliable reset signal generation through the simplified transistor-based voltage division and latching mechanism
Solution Approach 2:
The patent implements a self-service mechanism where the power-on reset circuit uses the supply voltage itself to generate the reset signal through passive voltage division and transistor switching, without requiring external reference signals or active comparison operations. This self-powered approach significantly reduces power consumption while ensuring reliable reset functionality
3Reliability
If the SR latch circuit output terminal is not held at a predetermined state during startup, then the circuit operates freely, but the power-on reset signal cannot maintain the reset state to reset the operating circuit
Solution Approach 1:
The patent applies preliminary action by configuring the SR latch circuit output terminal to be held at a predetermined state (either high or low) during the startup phase, before the enable signal becomes active. This preliminary state configuration ensures that the power-on reset signal maintains the correct level to force the operating circuit into the reset state, and the holding mechanism is automatically released when the enable signal transitions, allowing normal operation to resume
Data Source
AI summary
A Power-on Reset (POR) system includes: an SR latch circuit, powered by a supply voltage, for generating a POR signal according to the supply voltage and an enable signal; and at least one operating circuit, powered by the supply voltage. At least one state circuit in the operating circuit is reset by the POR signal. When the supply voltage starts up, an output terminal of the SR latch circuit has a predetermined state, such that after the supply voltage starts up and before the enable signal is enabled for a first time, the POR signal is in a reset state to reset the at least one state circuit in the operating circuit. After the supply voltage starts up and the enable signal is enabled for the first time, the POR signal turns to a non-reset state, and the operating circuit is enabled to operate according to the enable signal.