Wide-Voltage Level Shifter Circuit for Sub-Threshold Inputs
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Solution Overview
Problem
Conventional level shifters for integrated circuits are limited by their input to output voltage range, requiring large transistor devices and increasing semiconductor circuit area and power consumption, especially when shifting from low input voltages to high output voltages, and often necessitate additional supply voltages and multiple stages.
Innovation Solution
A single-stage level shifter circuit using a combination of NMOS and PMOS transistors, including a current mirror circuit, that operates across a wide voltage range without an intermediate voltage, minimizing area and power consumption while maintaining fast operation and low delays, even at sub-threshold input voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional level shifters are used to shift voltage from low to high domain, then voltage level shifting is achieved, but transistor device size must be large which increases circuit area and power consumption
Solution Approach 1:
The level shifter is divided into multiple stages: a first stage for voltage level shifting and a second stage for signal inversion. This segmentation allows each stage to be optimized independently, enabling the use of smaller transistors while achieving the desired voltage transition and signal polarity correction.
Solution Approach 2:
An intermediate voltage domain is introduced between the low voltage domain and high voltage domain. The first level shifter shifts voltage from low to intermediate domain, and the second level shifter shifts from intermediate to high domain. This intermediary approach allows using smaller transistors compared to direct low-to-high voltage shifting.
2Speed
If conventional level shifters operate at low input voltage to high output voltage, then voltage shifting is achieved, but operation speed is negatively impacted
Solution Approach 1:
The voltage shifting operation is segmented into two stages operating at different voltage domains. The first stage operates at low voltage with small transistors for fast switching, while the second stage operates at high voltage. This segmentation allows the circuit to achieve both low-power fast switching at low voltage and proper high-voltage signal output.
3Adaptability or versatility
If two or more voltage levels and multiple level shifting stages are used, then voltage range is extended, but extra supply voltages are required and area increases
Solution Approach 1:
The level shifter circuit is designed to handle multiple voltage transition scenarios (low-to-intermediate, intermediate-to-high, and low-to-high) using the same basic circuit architecture. The circuit can operate with different voltage combinations without requiring additional specialized circuits, achieving versatility through a universal design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a compact, low-power level shifter with minimal area requirements, capable of sub-threshold operation and reduced delays across a wide voltage range, with power consumption significantly lower than traditional architectures and superior delay performance.
Implementation Method 1
PMOS transistors M5 and M6 form a current mirror circuit
Data Source
AI summary
A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.