Clock Buffer Circuit with Shared Virtual Nodes for Faster Slew Rate
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Solution Overview
Problem
Existing semiconductor apparatuses experience a decrease in slew rate of clock signals due to drivers with transistors connected in series, leading to potential malfunctions in internal circuits, particularly for clock signals with periodic logic level changes.
Innovation Solution
A clock buffer circuit with two clock drivers, each including two transistors connected in series, where virtual nodes between these transistors are electrically connected, mitigating the decrease in slew rate by ensuring rapid transition slopes of rising and falling edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If transistors are connected in series in a driver circuit to enable activation control, then power consumption is reduced through power-gating, but the slew rate of the output clock signal decreases
Solution Approach 1:
The driver circuit is divided into two separate drivers (first clock driver and second clock driver) with independent transistor pairs. Each driver handles one clock signal path, allowing parallel operation that maintains slew rate while enabling power-gating control on each segment independently.
Solution Approach 2:
The first and second virtual ground nodes are electrically connected and merged into a common virtual ground node. This merging provides a shared reference potential that stabilizes the output signals and maintains fast transition edges, thereby preserving slew rate while allowing each driver to operate with activation control.
2Ease of operation
If transistors are connected in series in a driver circuit, then activation control function is enabled, but the transition slope of clock signals becomes slower
Solution Approach 1:
The circuit is segmented into two independent driver paths, each with its own series transistor configuration for activation control. This segmentation allows each path to maintain proper control functionality while the parallel structure prevents degradation of transition slopes.
Solution Approach 2:
The common virtual ground node acts as an intermediary that provides a stable reference potential for both drivers. This intermediary structure enables the series transistor configuration to maintain activation control while the shared reference prevents slowdown of transition slopes.
3Device complexity
If a simple driver structure is used, then device complexity is reduced, but signal loss increases
Solution Approach 1:
The virtual ground nodes of both drivers are merged into a common node, creating a shared reference structure that reduces overall circuit complexity. This merging provides signal reinforcement that compensates for losses in the series transistor configuration, maintaining signal integrity without adding complex compensation circuits.
Data Source
AI summary
A clock buffer circuit includes a first clock driver and a second clock driver. The first clock driver is configured to receive a first input clock signal and an enable signal to generate a first output clock signal. The second clock driver is configured to receive a second input clock signal and the enable signal to generate a second output clock signal. A virtual node of the first clock driver and a virtual node of the second clock driver are electrically connected to each other.