DDR5 Signal Receiver Latch Topology for Low-Delay Data Timing
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Solution Overview
Problem
Conventional circuit structures for signal receivers in DDR5 DRAM fail to meet the JEDEC specification due to large propagation delays and insufficient amplification of data signals, leading to mismatched requirements for data and data strobe signals.
Innovation Solution
A signal receiver design incorporating a series of current mode logic circuits and data latches, along with a data strobe signal receiver that amplifies and divides data signals to meet JEDEC standards, and a data latch structure utilizing differential pairs and feedback equalization to improve propagation delay and signal amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional circuit structure of signal receiver is used, then the device complexity is low, but the data signal amplification is insufficient and propagation delay does not meet JEDEC standards
Solution Approach 1:
The signal receiver is divided into multiple current mode logic circuits (CML circuits) connected in series, where each circuit stage provides incremental signal amplification and timing control. This segmentation allows the system to achieve the required propagation delay and signal amplification by distributing the function across multiple simpler stages rather than requiring a single complex circuit.
2Measurement precision
If the propagation delay between data receiver and data strobe signal receiver is increased, then the timing accuracy improves, but the device complexity increases
Solution Approach 1:
The patent introduces dynamic control mechanisms within the CML circuits, where bias currents and signal paths are dynamically adjusted to precisely control propagation delay. The differential pair structures and feedback mechanisms allow dynamic timing adjustment without requiring additional static delay elements, thereby achieving timing accuracy without proportionally increasing complexity.
3Reliability
If multiple CML circuits are connected in series to amplify data signal, then the signal amplification improves, but the device complexity increases
Solution Approach 1:
Multiple CML circuits are merged into a unified series architecture where each circuit stage shares common biasing and control mechanisms. The differential signal paths are merged through the series connection, allowing cumulative amplification effect while sharing control resources. This merging approach achieves reliable signal amplification without each stage requiring independent complex control circuits.
Data Source
AI summary
A signal receiver includes a data receiver and a data strobe signal receiver. The data receiver includes a plurality of current mode logic circuits and a plurality of data latches. A first stage current mode logic circuit receives a data signal, and a final stage current mode logic circuit outputs an amplified data signal. The plurality of data latches receive the amplified data signal, wherein each of the data latches sums the amplified data signal and a plurality of feedback data to obtain a summing data, and latches the summing data to output an output data according to one of a plurality of amplified data strobe signals. The data strobe signal receiver receives a data strobe signal, and generates the plurality of amplified data strobe signals by dividing a frequency of the data strobe signal.