Mixed-Signal MAC Circuit With ADC Bit Skipping for Edge AI
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Solution Overview
Problem
Existing digital processing units for matrix multiplication in machine learning algorithms, such as neural networks, are inefficient in terms of power consumption, particularly in edge computing devices, while analog MAC units based on switched capacitors offer greater efficiency but lose some efficiency during analog-to-digital conversion.
Innovation Solution
A mixed-signal circuit with switched capacitor-based MAC engines performs customized most significant bit (MSB) skipping and least significant bit (LSB) truncation during analog-to-digital conversion to preserve power efficiency and accuracy, using variable gain amplifiers and ADCs with customized bit reduction for each channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If digital processing units are used for matrix multiplication, then computational accuracy is maintained, but power consumption is excessive
Solution Approach 1:
The patent segments the computation process into analog MAC operations for multiplication and accumulation, followed by digital processing for final result computation. This segmentation allows the power-intensive digital processing to be minimized while maintaining accuracy through selective digital intervention only when necessary.
Solution Approach 2:
The patent introduces an intermediary mechanism where analog MAC units perform computations and a controller monitors signal characteristics to determine when digital processing is needed. This intermediary approach allows the system to operate primarily in analog mode for power efficiency while using digital processing only as needed to maintain accuracy.
2Use of energy by moving object
If analog MAC units based on switched capacitors are used, then power efficiency is improved, but precision is lost during analog-to-digital conversion
Solution Approach 1:
The patent applies partial action by performing analog-to-digital conversion only for the final accumulated results rather than for every intermediate computation. This allows the system to maintain power efficiency through analog processing while converting to digital only when precision is actually needed for the final output.
Solution Approach 2:
The patent changes the parameter of signal representation from continuous analog to discrete digital at strategically chosen points in the computation pipeline. By controlling when and how analog signals are converted to digital, the system maintains precision where needed while preserving power efficiency through extended analog processing.
3Measurement precision
If full precision analog-to-digital conversion is performed, then accuracy is maintained, but power efficiency is reduced
Solution Approach 1:
The patent applies local quality by using different precision levels for different parts of the computation pipeline. Analog MAC operations maintain high precision continuously, while analog-to-digital conversion uses reduced precision only when necessary, creating localized precision adjustments that optimize the overall power-accuracy tradeoff.
Solution Approach 2:
The patent performs partial analog-to-digital conversion by converting only the necessary portion of the computation results to digital format, rather than converting all intermediate and final results. This partial conversion approach maintains sufficient accuracy for the application while significantly reducing the power consumption associated with high-precision conversion operations.
Data Source
AI summary
A first integer value is split into a first coarse value and a first fine value, and a second integer value is split into a second coarse value and a second fine value. An analog multiply and accumulate (MAC) operation is performed on the first and second coarse values to produce a first analog output signal, an analog MAC operation is performed on the first coarse value and the second fine value to produce a second analog output signal, an analog MAC operation is performed on the first fine value and the second coarse value to produce a third analog output signal, and an analog MAC operation is performed on the first and second fine values to produce a fourth analog output signal. The first, second, third and fourth analog output signals are converted to first, second, third and fourth digital signals by first, second, third and fourth channels, respectively.