Latch-Based Power-On Reset Circuit for Low-Voltage Initialization
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Solution Overview
Problem
Existing power-on reset circuits in semiconductor apparatuses face issues with improper triggering or failure to trigger power-on resetting due to assumptions about power supply voltage thresholds or delay times, leading to unstable initialization of digital circuits.
Innovation Solution
A power-on reset circuit with a latch circuit and decision circuit that simulates the sequential circuit to be initialized, using cross-coupled inversion circuits to assert and negate a reset pulse based on the state of the latch circuit, allowing precise initialization without relying on large margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage scheme or delay scheme is used to trigger power-on resetting, then the reset circuit can be activated, but improper triggering or failure to trigger occurs when assumptions about voltage thresholds or delay times are not met
Solution Approach 1:
The patent creates a replica sequential circuit that copies the structure and behavior of the actual sequential circuit to be reset. This replica circuit experiences the same power-on conditions and transitions, allowing the reset trigger to be generated based on the replica's state rather than relying on assumptions about voltage thresholds or delay times. The reset signal is triggered when the replica circuit transitions from an undefined state to a stable state, ensuring reliable triggering under all power supply conditions.
2Reliability
If margin is saved to threshold or delay time to ensure triggering, then power-on resetting can be triggered, but the resetting cannot be triggered upon transition from undefined state to stable state
Solution Approach 1:
The patent uses the state of the replica sequential circuit as feedback to control the reset signal generation. The reset trigger is generated based on real-time monitoring of the replica circuit's transition from undefined to stable state, rather than using fixed voltage thresholds or delay times. This feedback mechanism ensures that the reset is triggered at the precise moment when the sequential circuit becomes stable, eliminating both premature and delayed resetting.
3Reliability
If voltage comparator is used to monitor power supply voltage, then voltage-based reset triggering can be achieved, but reset cannot be triggered unless power supply voltage exceeds minimum operating voltage of the comparator
Solution Approach 1:
Instead of using a voltage comparator that requires minimum operating voltage, the patent uses a replica sequential circuit that copies the behavior of the actual circuit. The replica circuit naturally responds to power-on conditions and voltage transitions without requiring external comparison, enabling the reset function to operate across a wider voltage range including below the minimum operating voltage of traditional comparators.
4Device complexity
If traditional voltage or delay scheme is used, then reset circuit structure is simple, but improper power-on resetting occurs when assumptions fail
Solution Approach 1:
The patent introduces a replica sequential circuit that copies the structure and behavior of the actual sequential circuit. This copying approach provides accurate reset triggering by observing the replica's state transitions, achieving high reliability without requiring complex voltage comparison logic or multiple delay circuits. The replica circuit naturally adapts to different power supply conditions, maintaining reliability while keeping the overall structure relatively simple.
Data Source
AI summary
A power-on reset circuit supplies a reset pulse to a sequential circuit to be initialized. A latch circuit includes a first inversion circuit and a second inversion circuit structured to invert and amplify a signal input thereto, with an output node of the first inversion circuit connected to an input node of the second inversion circuit, and with an output node of the second inversion circuit connected to an input node of the first inversion circuit. A decision circuit receives the first signal from the output node of the first inversion circuit and the second signal from the output node of the second inversion circuit and generates a reset pulse on the basis of the first signal and the second signal.