Floating-Point Adder Partitioning for Mixed-Sign Inputs
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Solution Overview
Problem
In designing hardware for processing units, particularly in mobile devices, there is a trade-off between power consumption, processing performance, and size, where improvements in one factor often result in worsening of another, and existing adder circuits for floating-point arithmetic do not efficiently handle sets of numbers with mixed signs.
Innovation Solution
The method involves identifying and adding together floating-point numbers with the same sign using same-sign floating-point adders, which are implemented in fixed function circuitry, and then using mixed-sign adders for the remaining calculations, optimizing the circuitry to reduce power consumption and silicon area while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a hardware implementation of floating-point addition is used, then processing performance is improved, but power consumption and silicon area increase
Solution Approach 1:
The adder circuit is segmented into multiple specialized units: a first same-sign adder for positive numbers, a second same-sign adder for negative numbers, and a mixed-sign adder. This segmentation allows each unit to be optimized for its specific function, reducing the overall complexity and resource requirements compared to a single general-purpose adder.
Solution Approach 2:
Different parts of the circuit have different functional properties tailored to their specific purposes. The same-sign adders are optimized for adding numbers with identical signs, while the mixed-sign adder handles cases with different signs. This local optimization reduces the computational overhead and resource consumption in each segment.
2Productivity
If a hardware implementation of floating-point addition is used, then processing performance is improved, but silicon area increases
Solution Approach 1:
The adder circuit is segmented into multiple specialized units: a first same-sign adder for positive numbers, a second same-sign adder for negative numbers, and a mixed-sign adder. This segmentation allows each unit to be optimized for its specific function, reducing the overall complexity and resource requirements compared to a single general-purpose adder.
Solution Approach 2:
The circuit uses a multiplexer to selectively route input pairs to appropriate adder units based on the sign bits of the operands. This multi-functional approach allows the same hardware resources to handle different addition cases (same-sign and mixed-sign), improving area efficiency while maintaining high processing performance.
3Device complexity
If existing adder circuits are used for floating-point arithmetic, then processing is simplified, but efficiency decreases when handling sets of numbers with mixed signs
Solution Approach 1:
The circuit performs preliminary classification of input pairs based on their sign bits before routing them to the appropriate adder unit. This preliminary action ensures that same-sign pairs are processed by optimized same-sign adders, improving overall processing efficiency without adding significant complexity to the control logic.
Solution Approach 2:
The circuit changes the operational parameters of the adder units based on the input characteristics. By detecting the sign bits of input numbers, the circuit dynamically selects which adder unit to use, effectively changing the operational mode to match the input data characteristics and thereby optimizing processing efficiency.
Data Source
AI summary
Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.