Delay-Chain Driving Buffer for 3DIC Overshoot Control

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Solution Overview

Problem

Long data transmission paths in integrated circuits, particularly in 3DICs, cause significant signal distortions leading to high error rates, which existing driving buffer designs struggle to address due to spatial constraints and high channel density requirements.

Innovation Solution

A driving buffer with configurable slew rate is implemented using transistors and delay chains to generate controllable rising and falling edges, employing multiple unit cells and selectors to produce optimized damping waveforms, allowing for tunable waveform shapes and reduced over/under-shooting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If long transmission paths are used in 3DIC devices, then data communication capability is improved, but signal distortion increases leading to high error rates

Engineering Contradiction:
Improvetransmission path lengthVSAvoiddata transmission error rate
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The transmission path is divided into multiple buffer stages (first buffer stage, second buffer stage, etc.) connected in series. Each stage processes the signal locally, preventing cumulative distortion over long distances. The segmentation allows the long transmission path to be managed as multiple shorter segments with controlled signal degradation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buffer stages are configured with different slew rates (first slew rate for rising edge, second slew rate for falling edge) that can be dynamically adjusted. This dynamic configuration optimizes signal waveform at each stage to compensate for distortion accumulated in previous stages, maintaining signal integrity over long transmission paths.

Inventive Principle:
Principle #15Dynamics

2Reliability

If driving buffer is added to compensate signal distortion, then data transmission reliability is improved, but spatial constraints and channel density requirements are worsened

Engineering Contradiction:
Improvedata transmission error rateVSAvoidspatial constraints and channel density
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Each buffer stage is designed to perform multiple functions: signal amplification, waveform shaping, and distortion compensation. The same buffer structure handles both rising and falling edges with different slew rates, eliminating the need for separate compensation circuits and reducing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Multiple buffer stages are nested in series within the transmission path, with each stage containing compact sub-circuits (transistors, delay chains, selectors). This nested arrangement allows efficient use of space by embedding functional blocks within each other, meeting spatial constraints while providing sufficient signal compensation.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Manufacturing precision

If configurable slew rate is implemented, then signal waveform control is improved reducing distortion, but device complexity increases

Engineering Contradiction:
Improvewaveform control precisionVSAvoidbuffer structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The buffer stages use different slew rate parameters (first slew rate for rising edge, second slew rate for falling edge) to optimize waveform control. By changing these electrical parameters rather than restructuring the entire circuit, precise waveform control is achieved with minimal increase in device complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Different parts of the buffer circuit are optimized for different functions: some transistors are sized for fast switching, others for precise slew rate control. The delay chains and selectors are locally configured to provide the specific timing and waveform shaping needed at each stage, rather than using a uniform design throughout.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12470205B2Driving buffer with configurable slew rate for data transmission
Publication Date: 2025.11.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12470205B2 patent drawing
  • US12470205B2 patent drawing
  • US12470205B2 patent drawing

AI summary

In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.