Reversible Current-Mirror Level Shifter for Subthreshold Logic
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Solution Overview
Problem
Voltage level shifters face challenges in maintaining operational speed when dealing with low supply voltages, as larger shifters required to accommodate these voltages consume more power and semiconductor surface area, and existing solutions are inadequate for subthreshold logic used in modern microcontrollers.
Innovation Solution
A low voltage level shifter employing a reversible current mirror circuit with NMOS transistors and PMOS transistors, which operates in forward and reverse modes to efficiently switch between low and high supply voltages, reducing transition delay and power consumption while occupying less semiconductor area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If larger voltage level shifters are used to accommodate lower supply voltages, then voltage compatibility is improved, but power consumption increases and semiconductor surface area increases
Solution Approach 1:
The patent changes the operating parameters of the transistors by implementing a reversible current mirror configuration that allows the level shifter to operate efficiently across a wide range of supply voltages including subthreshold voltages (0.1V-0.5V). The current mirror ratio and transistor sizing are optimized to maintain proper current relationships while minimizing power consumption and area.
2Adaptability or versatility
If larger voltage level shifters are used to accommodate lower supply voltages, then voltage compatibility is improved, but semiconductor surface area increases
Solution Approach 1:
The patent optimizes transistor dimensions and current mirror ratios to achieve proper voltage level shifting while minimizing the physical area occupied by the circuit. The reversible current mirror configuration allows for compact design by reusing transistor pairs for both forward and reverse voltage translation operations.
3Adaptability or versatility
If traditional voltage level shifters are used with low supply voltages, then voltage translation is achieved, but transition delay increases
Solution Approach 1:
The patent implements a reversible current mirror that can operate in both forward mode (translating from low voltage to high voltage) and reverse mode (translating from high voltage to low voltage). This bidirectional capability allows the circuit to quickly respond to voltage transitions in either direction, reducing transition delay compared to traditional unidirectional level shifters.
Solution Approach 2:
The reversible current mirror maintains continuous current flow and transistor conduction during voltage transitions, avoiding complete cutoff and recharge cycles. This continuous operation reduces the time required for voltage level transitions while maintaining accurate voltage translation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables faster operation and reduced power consumption while accommodating lower supply voltages, specifically suitable for subthreshold logic, with a transition delay of approximately 0.042 microseconds and reduced area requirements compared to traditional designs.
Implementation Method 1
A low voltage level shifter employs a reversible current mirror circuit with NMOS transistors and PMOS transistors, which operates in forward and reverse modes to efficiently switch between low and high supply voltages
Data Source
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AI summary
A low voltage level shifter (400) that is suitable for use with subthreshold logic. In one embodiment, the low voltage level shifter includes first and second input transistors (N11, N12) coupled to first and second input nodes (404, 406), respectively, that receive complementary low voltage input signals (in-l, inb-l). A circuit (402) is coupled to the first and second input transistors and to first and second output nodes (414, 412) that generate complementary high voltage output signals. The circuit is configured to transmit a first current (IP12) to the second output node (412) when the first input transistor (N11) is activated, wherein the first current is substantially equal to current drawn by the first input transistor when it is activated. The circuit is also configured to transmit a second current (IP14) to the first output node (414) when the second input transistor (N12) is activated, wherein the second current is substantially equal to current drawn by the second input transistor when it is activated.