EEPROM Decoder Latch Voltage Sequencing for Low-Voltage Stability
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Solution Overview
Problem
Current latch devices for EEPROM memories face challenges in operating at low voltages (Vdd ≤ 1.2 volts) due to conductivity imbalances between NMOS and PMOS transistors, leading to increased transistor size, gate capacitance, and unstable operation, which can result in premature aging and breakdown of gate oxides.
Innovation Solution
A compact CMOS RS latch flip-flop with a control module that manages voltage sequencing and positioning, allowing the latch to operate between a first and second supply voltage, including NOR gates, to output and maintain high or low voltages without causing prohibited logic states, thereby avoiding current conflicts and reducing gate oxide stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the latch device uses a 6-transistor SRAM scheme with adjusted W/L ratios to balance NMOS and PMOS conductivity, then the latch can operate at low voltages, but the transistor size increases and gate capacitance increases
Solution Approach 1:
The patent changes the fundamental operating parameters by using separate supply voltages for NMOS and PMOS transistors (Vsn and Vsp respectively), allowing each transistor type to operate optimally without requiring size adjustments. This parameter separation enables low voltage operation while maintaining compact transistor dimensions.
Solution Approach 2:
The latch device is segmented into two independent voltage domains: one for NMOS transistors (with supply voltage Vsn) and another for PMOS transistors (with supply voltage Vsp). This segmentation allows each transistor type to be optimized independently, avoiding the need to increase transistor size to compensate for conductivity imbalances.
2Ease of operation
If the latch device uses a 6-transistor SRAM scheme with adjusted W/L ratios to balance conductivity, then low voltage operation is enabled, but gate oxide stress increases leading to premature aging and breakdown
Solution Approach 1:
The patent introduces separate supply voltage parameters (Vsn for NMOS, Vsp for PMOS) that can be independently controlled. By optimizing these parameters, the voltage stress across gate oxides is reduced, preventing premature aging and breakdown while maintaining low voltage operation capability.
Solution Approach 2:
The patent introduces separate power supply networks as intermediary elements between the control logic and the transistors. These intermediary voltage sources (Vsn and Vsp) act as buffers that protect the gate oxides from excessive stress while enabling the latch to operate at low voltages.
3Ease of operation
If the latch device uses fast PMOS transistors with large channel width or slow NMOS transistors with large channel length to balance conductivity, then conductivity balance is achieved, but switching time increases
Solution Approach 1:
Instead of adjusting physical dimensions (channel length or width) to balance conductivity, the patent changes the electrical parameters by providing separate supply voltages (Vsn and Vsp). This allows fast switching because the transistors can be sized optimally for speed while the voltage parameters are tuned to achieve conductivity balance.
4Use of energy by moving object
If the latch device operates at low voltage Vdd to reduce power consumption, then power consumption decreases, but operation becomes unstable due to conductivity imbalances
Solution Approach 1:
The patent uses separate supply voltage parameters (Vsn and Vsp) that can be independently optimized to ensure stable operation at low power consumption. By tuning these parameters, the conductivity imbalances are compensated without requiring high voltages, maintaining operational stability while minimizing power usage.
Data Source
AI summary
The latch device includes an RS type latch flip-flop capable of being supplied between a first supply voltage and a second supply voltage which is lower than the first supply voltage and having first and second flip-flop inputs and a flip-flop output connected to the output terminal. A control module positions the latch flip-flop in a set state or in a reset state when the first supply voltage has a first value which is lower than the low voltage then, the latch flip-flop being positioned, confers the high voltage on the first supply voltage and the low voltage on the second supply voltage and outputs and maintains the high voltage or the low voltage on the flip-flop output while avoiding outputting a prohibited logic state at the two flip-flop inputs.