CMOS Logic Gate Parasitic Capacitance for On-Chip Power Stability
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Solution Overview
Problem
The increase in chip area and manufacturing cost due to the need for decoupling capacitors to stabilize power supply voltages in semiconductor devices, which restricts the effective use of semiconductor device area and increases costs.
Innovation Solution
The implementation of mode-switching MOSFETs that activate parasitic capacitances within the CMOS logic gates to stabilize power supply voltages without the need for additional decoupling capacitors, thereby reducing the chip area and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are provided on a chip to stabilize power supply voltages, then power supply stability is improved, but chip area increases
Solution Approach 1:
The patent utilizes the inherent parasitic capacitances already present in the CMOS logic gate structure (gate-to-source, gate-to-drain, and drain-to-substrate capacitances) to provide the decoupling function. By controlling the output signal level of the CMOS logic gate, these parasitic capacitances are activated to stabilize power supply voltages without requiring external decoupling capacitors, thus eliminating the need for additional chip area.
Solution Approach 2:
The patent makes the parasitic capacitances of the CMOS logic gate serve dual functions: maintaining the logic gate's normal logic operations and providing power supply decoupling/stabilization. By controlling the output signal level, the same structural elements (parasitic capacitances) perform both their original function and the additional decoupling function, eliminating the need for separate dedicated decoupling components.
2Reliability
If decoupling capacitors are provided on a chip to stabilize power supply voltages, then power supply stability is improved, but manufacturing cost increases
Solution Approach 1:
The patent utilizes the inherent parasitic capacitances already present in the CMOS logic gate structure (gate-to-source, gate-to-drain, and drain-to-substrate capacitances) to provide the decoupling function. By controlling the output signal level of the CMOS logic gate, these parasitic capacitances are activated to stabilize power supply voltages without requiring external decoupling capacitors, thus eliminating the need for additional chip area.
Solution Approach 2:
The patent makes the parasitic capacitances of the CMOS logic gate serve dual functions: maintaining the logic gate's normal logic operations and providing power supply decoupling/stabilization. By controlling the output signal level, the same structural elements (parasitic capacitances) perform both their original function and the additional decoupling function, eliminating the need for separate dedicated decoupling components.
3Area of stationary object
If mode-switching MOSFETs are used to activate parasitic capacitances, then chip area is reduced by eliminating decoupling capacitors, but device complexity increases
Solution Approach 1:
The patent utilizes the inherent parasitic capacitances already present in the CMOS logic gate structure (gate-to-source, gate-to-drain, and drain-to-substrate capacitances) to provide the decoupling function. By controlling the output signal level of the CMOS logic gate, these parasitic capacitances are activated to stabilize power supply voltages without requiring external decoupling capacitors, thus eliminating the need for additional chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively stabilizes power supply voltages while minimizing the increase in chip area and manufacturing costs by utilizing the existing parasitic capacitances of the CMOS logic gates, reducing the number of additional MOSFETs required and eliminating the need for decoupling capacitors.
Implementation Method 1
a MOSFET configured to give a potential difference to a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate
Data Source
AI summary
A semiconductor device of an embodiment includes: a power supply line and a ground line; a CMOS logic gate including a P-type MOSFET network connected to the power supply line, and an N-type MOSFET network connected to a ground line side of the P-type MOSFET network; and a P-type MOSFET and an N-type MOSFET configured to activate a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate.