Spike Generation Circuit With Delayed Inverter Pulse Gating
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Solution Overview
Problem
Spike generator circuits, such as those used in neural networks, face challenges in reducing power consumption while maintaining efficient spike signal generation.
Innovation Solution
The proposed spike generation circuit incorporates a CMOS inverter, a switch, an inverting circuit, and a delay circuit, with specific configurations of CMOS inverters and capacitance elements to control signal inversion and delay, resulting in a spike signal with a narrow pulse width and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional spike generator circuits are used, then spike signal generation is achieved, but power consumption is high
Solution Approach 1:
The circuit is divided into multiple functional blocks: a first CMOS inverter for signal inversion, a delay circuit for timing control, and a second CMOS inverter for spike generation. This segmentation allows each block to perform its function efficiently, reducing overall power consumption while maintaining reliable spike signal generation.
Solution Approach 2:
The circuit uses periodic switching of the power supply voltage to the first CMOS inverter based on the input signal transitions. The inverter is activated only when needed (on rising or falling edges), and remains inactive otherwise, creating a periodic action pattern that significantly reduces average power consumption while maintaining spike generation capability.
2Use of energy by moving object
If the pulse width of spike signals is reduced, then power consumption decreases, but rise and fall times become insufficiently steep
Solution Approach 1:
The delay circuit acts as an intermediary between the input signal and the second CMOS inverter. It introduces a precise time delay that controls the duration of the spike signal without affecting the steepness of rise and fall times. This mediator allows the circuit to produce narrow pulses with sharp transitions by coordinating the activation timing of the second inverter.
Solution Approach 2:
The circuit changes the operating parameters of the CMOS inverters dynamically. The first inverter switches its power supply voltage between active and inactive states based on signal edges, and the delay circuit adjusts the timing parameters. These parameter changes enable the generation of spikes with both narrow width and steep transitions by optimizing the voltage and timing characteristics.
Data Source
AI summary
A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.